ST72F63BK1M1 STMicroelectronics, ST72F63BK1M1 Datasheet - Page 54
ST72F63BK1M1
Manufacturer Part Number
ST72F63BK1M1
Description
IC MCU 8BIT 4K FLASH 34-SOIC
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F63BD6U1TR.pdf
(186 pages)
Specifications of ST72F63BK1M1
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SCI, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
19
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 12x8b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
34-SOIC (7.5mm Width)
Processor Series
ST72F6x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
I2C, SCI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
19
Number Of Timers
1
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7MDTU3-EPB/US, ST72F63B-SK/RAIS, ST7MDTU3-EMU3, STX-RLINK
Minimum Operating Temperature
0 C
On-chip Adc
8 bit, 8 Channel / 8 bit, 12 Channel
For Use With
497-5521 - EVAL BOARD LOW SPEED USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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On-chip peripherals
11
11.1
11.1.1
11.1.2
11.1.3
54/186
On-chip peripherals
Watchdog timer (WDG)
Introduction
The Watchdog timer is used to detect the occurrence of a software fault, usually generated
by external interference or by unforeseen logical conditions, which causes the application
program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on
expiry of a programmed time period, unless the program refreshes the counter’s contents
before the T6 bit becomes cleared.
Main features
●
●
●
●
●
Functional description
The counter value stored in the CR register (bits T6:T0), is decremented every 49,152
machine cycles, and the length of the timeout period can be programmed by the user in 64
increments.
If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T6:T0) rolls
over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle by driving low the reset
pin for t
The application program must write in the CR register at regular intervals during normal
operation to prevent an MCU reset. This down counter is free-running: it counts down even if
the watchdog is disabled. The value to be stored in the CR register must be between FFh
and C0h (see
●
●
●
Programmable free-running counter (64 increments of 49,152 CPU cycles)
Programmable reset
Reset (if watchdog activated) when the T6 bit reaches zero
Optional reset on HALT instruction (configurable by option byte)
Hardware Watchdog selectable by option byte.
The WDGA bit is set (watchdog enabled)
The T6 bit is set to prevent generating an immediate reset
The T5:T0 bits contain the number of increments which represents the time delay
before the watchdog produces a reset.
W(RSTL)out
Table
(see
17):
Table
72).
Doc ID 7516 Rev 8
ST7263Bxx
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