Z8F0823PJ005SG Zilog, Z8F0823PJ005SG Datasheet - Page 60

• Manufacturer Part Number: Z8F0823PJ005SG
• Description: IC ENCORE MCU FLASH 8K 28-DIP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0823PJ005SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 269-4218; Z8F0823PJ005SG

BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
PS025203-0405
Table 24. Port A–C STOP Mode Recovery Source Enable Sub-Registers (PxSMRE)
PSMRE7
PHDE7
R/W
R/W
If 04H in Port A–C Address Register, accessible through the Port A–C Control Register
If 05H in Port A–C Address Register, accessible through the Port A–C Control Register
0
0
7
7
Port A–C High Drive Enable Sub-Registers
The Port A–C High Drive Enable sub-register (Table 23) is accessed through the Port
A–C Control register by writing
the Port A–C High Drive Enable sub-registers to 1 configures the specified port pins for
high current output drive operation. The Port A–C High Drive Enable sub-register affects
the pins directly and, as a result, alternate functions are also affected.
PHDE[7:0]—Port High Drive Enabled
0 = The Port pin is configured for standard output current drive.
1 = The Port pin is configured for high output current drive.
Port A–C STOP Mode Recovery Source Enable Sub-Registers
The Port A–C STOP Mode Recovery Source Enable sub-register (Table 24) is accessed
through the Port A–C Control register by writing
Setting the bits in the Port A–C STOP Mode Recovery Source Enable sub-registers to 1
configures the specified Port pins as a STOP Mode Recovery source. During STOP Mode,
any logic transition on a Port pin enabled as a STOP Mode Recovery source initiates
STOP Mode Recovery.
PSMRE[7:0]—Port STOP Mode Recovery Source Enabled
0 = The Port pin is not configured as a STOP Mode Recovery source. Transitions on this
pin during STOP mode do not initiate STOP Mode Recovery.
1 = The Port pin is configured as a STOP Mode Recovery source. Any logic transition on
this pin during STOP mode initiates STOP Mode Recovery.
Table 23. Port A–C High Drive Enable Sub-Registers (PxHDE)
PSMRE6
PHDE6
R/W
R/W
6
0
6
0
PSMRE5
PHDE5
R/W
R/W
5
0
5
0
P R E L I M I N A R Y
PSMRE4
PHDE4
04H
R/W
R/W
0
0
4
4
to the Port A–C Address register. Setting the bits in
PSMRE3
PHDE3
R/W
R/W
3
0
3
0
05H
to the Port A–C Address register.
PSMRE2
PHDE2
Z8 Encore!
R/W
R/W
0
0
2
2
Product Specification
PSMRE1
PHDE1
®
R/W
R/W
General-Purpose I/O
1
0
1
0
Z8F0823 Series
PSMRE0
PHDE0
R/W
R/W
0
0
0
0
43