Z8F0823PJ005SG Zilog, Z8F0823PJ005SG Datasheet - Page 111

• Manufacturer Part Number: Z8F0823PJ005SG
• Description: IC ENCORE MCU FLASH 8K 28-DIP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0823PJ005SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 269-4218; Z8F0823PJ005SG

PS025203-0405
DE
1
0
1
0
Idle State
of Line
UART Interrupts
Figure 14.UART Driver Enable Signal Timing (shown with 1 Stop Bit and Parity)
⎛
⎝
------------------------------------ -
Baud Rate (Hz)
asserts at least one UART bit period and no greater than two UART bit periods before the
Start bit is transmitted. This allows a setup time to enable the transceiver. The Driver
Enable signal deasserts one system clock period after the final Stop bit is transmitted. This
one system clock delay allows both time for data to clear the transceiver before disabling
it, as well as the ability to determine if another character follows the current character. In
the event of back to back characters (new data must be written to the Transmit Data Regis-
ter before the previous character is completely transmitted) the DE signal is not deasserted
between characters. The Depol bit in the UART Control Register 1 sets the polarity of the
Driver Enable signal.
The Driver Enable to Start bit setup time is calculated as follows:
The UART features separate interrupts for the transmitter and the receiver. In addition,
when the UART primary functionality is disabled, the Baud Rate Generator can also func-
tion as a basic timer with interrupt capability.
Transmitter Interrupts
The transmitter generates a single interrupt when the Transmit Data Register Empty bit
(TDRE) is set to 1. This indicates that the transmitter is ready to accept new data for trans-
mission. The TDRE interrupt occurs after the Transmit shift register has shifted the first
bit of data out. The Transmit Data register can now be written with the next character to
send. This action provides 7 bit periods of latency to load the Transmit Data register
before the Transmit shift register completes shifting the current character. Writing to the
UART Transmit Data register clears the TDRE bit to 0.
Start
1
Bit0
lsb
Bit1
⎞
⎠
≤
DE to Start Bit Setup Time (s)
Bit2
P R E L I M I N A R Y
Bit3
Data Field
Bit4
Bit5
Bit6
≤
⎛
⎝
Z8 Encore!
------------------------------------ -
Baud Rate (Hz)
msb
Bit7
Product Specification
2
Parity
®
Z8F0823 Series
Stop Bit
⎞
⎠
1
UART
94