ST7FLITE35M6TR STMicroelectronics, ST7FLITE35M6TR Datasheet - Page 68
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ST7FLITE35M6TR
Manufacturer Part Number
ST7FLITE35M6TR
Description
IC MCU 8BIT 8K FLASH 20SOIC
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST7FLITE35F2M6TR.pdf
(173 pages)
Specifications of ST7FLITE35M6TR
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
LINSCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Processor Series
ST7FLITE3x
Core
ST7
Data Bus Width
8 bit
Development Tools By Supplier
ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
For Use With
497-5858 - EVAL BOARD PLAYBACK ST7FLITE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
- Current page: 68 of 173
- Download datasheet (3Mb)
ST7LITE3xF2
DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d)
AUTORELOAD REGISTER (ATR1H)
Read / Write
Reset Value: 0000 0000 (00h)
AUTORELOAD REGISTER (ATR1L)
Read / Write
Reset Value: 0000 0000 (00h)
Bits 11:0 = ATR1[11:0] Autoreload Register 1.
This is a 12-bit register which is written by soft-
ware. The ATR1 register value is automatically
loaded into the upcounter CNTR1 when an over-
flow occurs. The register value is used to set the
PWM frequency.
PWM OUTPUT CONTROL REGISTER
(PWMCR)
Read/Write
Reset Value: 0000 0000 (00h)
Bits 7:0 = OE[3:0] PWMx output enable.
These bits are set and cleared by software and
cleared by hardware after a reset.
0: PWM mode disabled. PWMx Output Alternate
1: PWM mode enabled
68/173
1
ATR7
15
Function disabled (I/O pin free for general pur-
pose I/O)
0
7
7
0
ATR6
OE3
0
ATR5
0
0
ATR4
OE2
0
ATR11 ATR10 ATR9
ATR3
0
ATR2
OE1
ATR1
0
ATR0
ATR8
OE0
0
0
8
PWMx CONTROL STATUS REGISTER
(PWMxCSR)
Read / Write
Reset Value: 0000 0000 (00h)
Bits 7:2= Reserved, must be kept cleared.
Bit 1 = OPx PWMx Output Polarity.
This bit is read/write by software and cleared by
hardware after a reset. This bit selects the polarity
of the PWM signal.
0: The PWM signal is not inverted.
1: The PWM signal is inverted.
Bit 0 = CMPFx PWMx Compare Flag.
This bit is set by hardware and cleared by software
by reading the PWMxCSR register. It indicates
that the upcounter value matches the Active DCRx
register value.
0: Upcounter value does not match DCRx value.
1: Upcounter value matches DCRx value.
BREAK CONTROL REGISTER (BREAKCR)
Read/Write
Reset Value: 0000 0000 (00h)
Bits 7:6 = Reserved. Forced by hardware to 0.
Bit 5 = BA Break Active.
This bit is read/write by software, cleared by hard-
ware after reset and set by hardware when the
BREAK pin is low. It activates/deactivates the
Break function.
0: Break not active
1: Break active
7
0
7
0
6
0
0
BA
0
BPEN
0
PWM3 PWM2 PWM1 PWM0
0
0
OPx
CMPFx
0
0
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