Z8PE003SZ010EG Zilog, Z8PE003SZ010EG Datasheet - Page 21

• Manufacturer Part Number: Z8PE003SZ010EG
• Description: IC MICROCONTROLLER 1K 18-SOIC
• Manufacturer: Zilog
• Series: Z8® Plusr

Specifications of Z8PE003SZ010EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Size: 1KB (1K x 8)
• Program Memory Type: OTP
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 18-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Other names: 269-4294; Z8PE003SZ010EG

ZiLOG
WATCH-DOG TIMER
The Watch-Dog Timer (
16-bit timer that resets the device if it reaches its terminal
count. The
vide the longer time-out periods required in applications,
the watch-dog timer is only updated every 64th clock cycle.
When operating in the
out reset is functionally equivalent to an interrupt vectoring
the PC to
out of
value set at minimum, unless otherwise programmed during
the first instruction. Subsequent executions of the
struction reinitialize the watch-dog timer registers (
C3h
D4
cept on the first cycle after
ters
DS007500-Z8X0399
of the
) to their initial values as defined by bits
STOP
0C1
RESET
D7
TCTLHI
*Designates the default value after RESET.
0020H
mode.
WDT
, the
D6
is driven by the
, and setting the
register. The
WDT
RUN
D5
WDT
is fully enabled with its time-out
RESET
or
) is a retriggerable one-shot
WDT
HALT
D4
XTAL2
WDT
and when the device en-
Figure 11. TCTLHI Register for Control of WDT
cannot be disabled ex-
modes, a
TCTLHI
flag to
clock pin. To pro-
D3
D6
WDT
1
. Coming
D2
,
P R E L I M I N A R Y
WDT
C2h
D5
time-
, and
and
in-
D1
The
provide some margin of time to allow the
approach
tively long, a
the
instruction is executed.
RESET
out sets the
SMR
whether a
curred. Reading the
flag to
Note: Failure to clear the
D0
WDT
WDT
flag. This function enables software to determine
0
behavior.
clears both the
; therefore, the user must clear the flag via software.
times out on exactly the same cycle that the
0
WDT
instruction should be executed often enough to
. Because the
WDT
WDT RESET
Reserved (must be 0)
0 = STOP mode enabled
1 = STOP mode disabled*
D6 D5 D4 WDT TIMEOUT VALUE
---- ---- ---- --------------------------------
(XTAL clocks to time-out)
0
0
0
0
1
1
1
1
1 = WDT enabled in HALT mode*
0 = WDT disabled in HALT mode
time-out or a return from
flag, and the
WDT
0
0
1
1
0
0
1
1
WDT
0
1
0
1
0
1
0
1
SMR
WDT
and
occurs in the unlikely event that
Z8Plus OTP Microcontroller
and
SMR
1,048,576 TpC
2,097,152 TpC
8,388,608 TpC
flag can result in unexpected
time-out periods are rela-
STOP
131,072 TpC
262,144 TpC
524,288 TpC
SMR
65,536 TpC*
flags does not reset the
Disabled
flags. A
instruction sets the
WDT
STOP
WDT
registers to
mode oc-
Z8PE003
WDT
time-
21