Z8PE003SZ010EG Zilog, Z8PE003SZ010EG Datasheet - Page 20

• Manufacturer Part Number: Z8PE003SZ010EG
• Description: IC MICROCONTROLLER 1K 18-SOIC
• Manufacturer: Zilog
• Series: Z8® Plusr

Specifications of Z8PE003SZ010EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Size: 1KB (1K x 8)
• Program Memory Type: OTP
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 18-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Other names: 269-4294; Z8PE003SZ010EG

Z8PE003
Z8Plus OTP Microcontroller
IREQ SOFTWARE INTERRUPT GENERATION
IREQ
ifying
the Z8Plus Standard Register File. These software inter-
rupts (
generated requests. In other words, the
enabling of each
To generate a
lowing statement:
The immediate data variable,
position corresponding to the required level of
ample, an
5
If the interrupt system is globally enabled,
abled, and there are no higher priority requests pending,
control is transferred to the service routine pointed to by the
IREQ5
Note: Software may modify the
PROGRAMMABLE OPTIONS
EPROM Protect.
PROTECT/ENABLE TESTMODE
the software code in the program memory. ZiLOG’s inter-
nal factory test mode, or any of the standard test mode meth-
ods, are useful for reading or verifying the code in the mi-
crocontroller when using an EPROM programmer. If the
user should select the
ABLE TESTMODE
using a tester, programmer, or any other standard method.
As a result, ZiLOG is unable to test the EPROM memory
at any time after customer delivery.
20
of
NUMBER
OR IREQ,#NUMBER
OR IREQ, #00100000B
can be used to generate software interrupts by spec-
IREQ
SWI
should be taken when using any instruction that modifies
the
software writeback always takes precedence over the
hardware. If a software writeback takes place on the
same cycle as an interrupt source tries to set an
the new interrupt is lost.
vector.
SWI
IREQ
) are controlled in the same manner as hardware
as the destination of any instruction referencing
SWI
must be issued when an
must have a value of
register while interrupt sources are active. The
SWI
When selecting the
, the request bit in
option, it is not possible to read the code
.
ENABLE EPROM PROTECT/DIS-
NUMBER
IREQ
option, the user can read
register at any time. Care
IREQ
1
.
IMASK
DISABLE EPROM
, has a
IREQ5
is set by the fol-
IREQ5
SWI
controls the
1
occurs. Bit
in the bit
P R E L I M I N A R Y
IREQ
. For ex-
is en-
bit,
Nesting of Vectored Interrupts
Nesting vectored interrupts allows higher priority requests
to interrupt a lower priority request. To initiate vectored in-
terrupt nesting, perform the following steps during the in-
terrupt service routine:
•
•
•
•
•
•
•
Depending on the application, some simplification of the
above procedure may be possible.
RESET Conditions
The
This option bit only affects the user’s ability to read the code
and has no effect on the operation of the part in an appli-
cation. ZiLOG tests the EPROM memory before customer
delivery whether or not the
TECT/DISABLE TESTMODE
provides a standard warranty for the part.
System Clock Source.
TOR ENABLE
controller is configured to work with an external RC circuit.
When selecting the Crystal/Other Clock Source option, the
oscillator circuit is configured to work with an external
crystal, ceramic resonator, or LC oscillator.
PUSH
Load
ity interrupts
Execute an
Proceed with interrupt processing
Execute a
Restore the
previous mask from the stack
Execute
IMASK
IMASK
the old
and
IRET
DI
option, the oscillator circuit on the micro-
EI
IMASK
IREQ
instruction after processing is complete
with a new mask to disable lower prior-
instruction
IMASK
registers initialize to
to its original value by
When selecting the
on the stack
option is selected; ZiLOG
ENABLE EPROM PRO-
DS007500-Z8X0399
00h
RC OSCILLA-
POP
on
RESET
ZiLOG
ing the
.