ST72F63BE1M1 STMicroelectronics, ST72F63BE1M1 Datasheet - Page 106
ST72F63BE1M1
Manufacturer Part Number
ST72F63BE1M1
Description
IC MCU 8BIT 4K FLASH 24-SOIC
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F63BD6U1TR.pdf
(186 pages)
Specifications of ST72F63BE1M1
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SCI, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
14
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
24-SOIC (7.5mm Width)
Data Converters
A/D 12x8b
Processor Series
ST72F6x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
I2C, SCI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
14
Number Of Timers
1
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7MDTU3-EPB/US, ST7MDTULS-EVAL, ST72F63B-SK/RAIS, ST7MDTU3-EMU3, STX-RLINK
Minimum Operating Temperature
0 C
For Use With
497-5521 - EVAL BOARD LOW SPEED USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
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Part Number
Manufacturer
Quantity
Price
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On-chip peripherals
11.4.5
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Endpoint 0 register B (EP0RB)
This register is used for controlling data reception on Endpoint 0. It is also reset by the USB
bus reset.
Reset value: 1000 0000 (80h)
Programming considerations
The interaction between the USB interface and the application program is described below.
Apart from system reset, action is always initiated by the USB interface, driven by one of the
USB events associated with the Interrupt Status register (ISTR) bits.
Initializing the registers
At system reset, the software must initialize all registers to enable the USB interface to
properly generate interrupts and DMA requests.
1.
2.
3.
4.
Initializing DMA buffers
The DMA buffers are a contiguous zone of memory whose maximum size is 48 bytes. They
can be placed anywhere in the memory space to enable the reception of messages. The 10
most significant bits of the start of this memory area are specified by bits DA15-DA6 in
registers DMAR and IDR, the remaining bits are 0. The memory map is shown in
Each buffer is filled starting from the bottom (last 3 address bits=000) up.
Endpoint Initialization
To be ready to receive, set STAT_RX to VALID (11b) in EP0RB to enable reception.
To be ready to transmit:
1.
2.
3.
Initialize the DMAR, IDR, and IMR registers (choice of enabled interrupts, address of
DMA buffers). Refer the paragraph titled initializing the DMA Buffers.
Initialize the EP0RA and EP0RB registers to enable accesses to address 0 and
endpoint 0 to support USB enumeration. Refer to the paragraph titled Endpoint
Initialization.
When addresses are received through this channel, update the content of the DADDR.
If needed, write the endpoint numbers in the EA fields in the EP1RB and EP2RB
register.
Write the data in the DMA transmit buffer.
In register EPnRA, specify the number of bytes to be transmitted in the TBC field
Enable the endpoint by setting the STAT_TX bits to VALID (11b) in EPnRA.
7
1
[6:4] Refer to the EPnRB register for a description of these bits.
[3:0] Forced by hardware to 0.
7 Forced by hardware to 1.
DTOG
RX
STAT
RX1
Doc ID 7516 Rev 8
STAT
RX0
Read.write
0
0
0
ST7263Bxx
Figure
0
0
45.
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