ST7FLIT15BM6TR STMicroelectronics, ST7FLIT15BM6TR Datasheet - Page 46

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ST7FLIT15BM6TR

Manufacturer Part Number
ST7FLIT15BM6TR
Description
IC MCU 8BIT 2K FLASH SOIC
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet

Specifications of ST7FLIT15BM6TR

Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
ST7FLIT1x
Core
ST7
Data Bus Width
8 bit
Development Tools By Supplier
ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
For Use With
497-5049 - KIT STARTER RAISONANCE ST7FLITE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Package / Case
-
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ST7FLIT15BM6TR
Manufacturer:
ST
0
Part Number:
ST7FLIT15BM6TR
Manufacturer:
ST
Quantity:
20 000
ST7LITE1xB
POWER SAVING MODES (Cont’d)
Figure 31. AWUFH Mode Flow-chart
46/159
1
(AWUCSR.AWUEN=1)
HALT INSTRUCTION
(Active-Halt disabled)
N
WATCHDOG
WDGHALT
RESET
1
INTERRUPT
Y
1)
ENABLE
3)
256 OR 4096 CPU CLOCK
OR SERVICE INTERRUPT
0
FETCH RESET VECTOR
AWU RC OSC
AWU RC OSC
MAIN OSC
PERIPHERALS
CPU
MAIN OSC
PERIPHERALS
CPU
AWU RC OSC
MAIN OSC
PERIPHERALS
CPU
I[1:0] BITS
I[1:0] BITS
I[1:0] BITS
N
CYCLE
RESET
Y
WATCHDOG
DELAY
DISABLE
2)
XX
XX
OFF
OFF
OFF
OFF
OFF
OFF
ON
ON
5)
ON
ON
ON
ON
10
4)
4)
Notes:
1. WDGHALT is an option bit. See option byte sec-
tion for more details.
2. Peripheral clocked with an external clock source
can still be active.
3. Only an AWUFH interrupt and some specific in-
terrupts can exit the MCU from HALT mode (such
as external interrupt). Refer to Table 5, “Interrupt
Mapping,” on page 37 for more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.
5. If the PLL is enabled by option byte, it outputs
the clock after an additional delay of t
Figure
13).
STARTUP
(see

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