ST7FLIT15BF1M6 STMicroelectronics, ST7FLIT15BF1M6 Datasheet - Page 72
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ST7FLIT15BF1M6
Manufacturer Part Number
ST7FLIT15BF1M6
Description
IC MCU 8BIT 4K FLASH 20-SOIC
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST7FLIT15BY1M6.pdf
(159 pages)
Specifications of ST7FLIT15BF1M6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Processor Series
ST7FLIT1x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
17
Number Of Timers
4
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 7 Channel
For Use With
497-5049 - KIT STARTER RAISONANCE ST7FLITE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST7FLIT15BF1M6
Manufacturer:
ST
Quantity:
8 567
Part Number:
ST7FLIT15BF1M6
Manufacturer:
ST
Quantity:
20 000
ST7LITE1xB
DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d)
11.2.6 Register Description
TIMER CONTROL STATUS REGISTER
(ATCSR)
Read / Write
Reset Value: 0x00 0000 (x0h)
Bit 7 = Reserved.
Bit 6 = ICF Input Capture Flag.
This bit is set by hardware and cleared by software
by reading the ATICR register (a read access to
ATICRH or ATICRL will clear this flag). Writing to
this bit does not change the bit value.
0: No input capture
1: An input capture has occurred
Bit 5 = ICIE IC Interrupt Enable.
This bit is set and cleared by software.
0: Input capture interrupt disabled
1: Input capture interrupt enabled
Bits 4:3 = CK[1:0] Counter Clock Selection.
These bits are set and cleared by software and
cleared by hardware after a reset. They select the
clock frequency of the counter.
Bit 2 = OVF1 Overflow Flag.
This bit is set by hardware and cleared by software
by reading the ATCSR register. It indicates the
transition of the counter1 CNTR1 from FFFh to
ATR1 value.
0: No counter overflow occurred
1: Counter overflow occurred
72/159
1
7
0
f
LTIMER
Counter Clock Selection
ICF
(1 ms timebase @ 8 MHz)
ICIE
32 MHz
OFF
f
CPU
CK1
CK0
OVF1 OVFIE1 CMPIE
CK1
0
1
0
1
CK0
0
1
1
0
0
Bit 1 = OVFIE1 Overflow Interrupt Enable.
This bit is read/write by software and cleared by
hardware after a reset.
0: Overflow interrupt disabled.
1: Overflow interrupt enabled.
Bit 0 = CMPIE Compare Interrupt Enable.
This bit is read/write by software and cleared by
hardware after a reset. It can be used to mask the
interrupt generated when any of the CMPFx bit is
set.
0: Output compare interrupt disabled.
1: Output Compare interrupt enabled.
COUNTER REGISTER 1 HIGH (CNTR1H)
Read only
Reset Value: 0000 0000 (00h)
COUNTER REGISTER 1 LOW (CNTR1L)
Read only
Reset Value: 0000 0000 (00h)
Bits 15:12 = Reserved.
Bits 11:0 = CNTR1[11:0] Counter Value.
This 12-bit register is read by software and cleared
by hardware after a reset. The counter CNTR1 in-
crements continuously as soon as a counter clock
is selected. To obtain the 12-bit value, software
should read the counter value in two consecutive
read operations. As there is no latch, it is recom-
mended to read LSB first. In this case, CNTR1H
can be incremented between the two read opera-
tions and to have an accurate result when
CNTR1L values close to FFh are read.
When a counter overflow occurs, the counter re-
starts from the value specified in the ATR1 regis-
ter.
CNTR1_
f
timer
15
0
7
7
=f
CNTR1_
CPU
0
6
, special care must be taken when
CNTR1_
0
5
CNTR1_
0
4
CNTR1_
CNTR1_
11
3
CNTR1_
CNTR1_
10
2
CNTR1_
CNTR1_
9
1
CNTR1_
CNTR1_
8
8
0
0