ST7FLITE09M6TR STMicroelectronics, ST7FLITE09M6TR Datasheet - Page 57

• Manufacturer Part Number: ST7FLITE09M6TR
• Description: IC MCU 8BIT FLASH 16SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITE09M6TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI
• Peripherals: PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 1.5KB (1.5K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 5x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC
• Processor Series: ST7FLITE0x
• Core: ST7
• Data Bus Width: 8 bit
• Development Tools By Supplier: ST7FLIT0-IND/USB, ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• For Use With: 497-5858 - EVAL BOARD PLAYBACK ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12-BIT AUTORELOAD TIMER (Cont’d)
AUTO RELOAD REGISTER (ATRH)
Read / Write
Reset Value: 0000 0000 (00h)
AUTO RELOAD REGISTER (ATRL)
Read / Write
Reset Value: 0000 0000 (00h)
Bits 15:12 = Reserved, must be kept cleared.
Bits 11:0 = ATR[11:0] Autoreload Register.
This is a 12-bit register which is written by soft-
ware. The ATR register value is automatically
loaded into the upcounter when an overflow oc-
curs. The register value is used to set the PWM
frequency.
PWM0 DUTY CYCLE REGISTER HIGH (DCR0H)
Read / Write
Reset Value: 0000 0000 (00h)
ATR7
15
15
0
7
0
ATR6
0
0
ATR5
0
0
ATR4
0
0
DCR11 DCR10 DCR9 DCR8
ATR11 ATR10 ATR9
ATR3
ATR2
ATR1
ATR0
ATR8
0
8
8
PWM0 DUTY CYCLE REGISTER LOW (DCR0L)
Read / Write
Reset Value: 0000 0000 (00h)
Bits 15:12 = Reserved, must be kept cleared.
Bits 11:0 = DCR[11:0] PWMx Duty Cycle Value
This 12-bit value is written by software. The high
register must be written first.
In PWM mode (OE0=1 in the PWMCR register)
the DCR[11:0] bits define the duty cycle of the
PWM0 output signal (see
Compare mode, (OE0=0 in the PWMCR register)
they define the value to be compared with the 12-
bit upcounter value.
PWM0
(PWM0CSR)
Read / Write
Reset Value: 0000 0000 (00h)
Bit 7:2= Reserved, must be kept cleared.
Bit 1 = OP0 PWM0 Output Polarity.
This bit is read/write by software and cleared by
hardware after a reset. This bit selects the polarity
of the PWM0 signal.
0: The PWM0 signal is not inverted.
1: The PWM0 signal is inverted.
Bit 0 = CMPF0 PWM0 Compare Flag.
This bit is set by hardware and cleared by software
by reading the PWM0CSR register. It indicates
that the upcounter value matches the DCR0 regis-
ter value.
0: Upcounter value does not match DCR value.
1: Upcounter value matches DCR value.
DCR7 DCR6 DCR5 DCR4 DCR3 DCR2 DCR1 DCR0
7
7
0
0
CONTROL/STATUS
0
ST7LITE0xY0, ST7LITESxY0
0
Figure
0
0
35). In Output
REGISTER
OP0 CMPF0
57/124
0
0
1