ST7FLIT10BF1M6 STMicroelectronics, ST7FLIT10BF1M6 Datasheet - Page 103
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ST7FLIT10BF1M6
Manufacturer Part Number
ST7FLIT10BF1M6
Description
IC MCU 8BIT 4K FLASH 20-SOIC
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST7FLIT15BY1M6.pdf
(159 pages)
Specifications of ST7FLIT10BF1M6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Processor Series
ST7FLIT1x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
17
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 7 Channel
For Use With
497-5049 - KIT STARTER RAISONANCE ST7FLITE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
ANALOG COMPARATOR (Cont’d)
Bit 4 = CMPIF Comparator Interrupt Flag
This bit is set by hardware when interrupt is gener-
ated at the rising edge (CINV = 0) or falling edge
(CINV = 1) of comparator output. This bit is
cleared by reading the CMPCR register. Writing to
this bit does not change the value.
0 : Comparator interrupt flag cleared
1 : Comparator interrupt flag set and can generate
Bit 3 : CMPIE Comparator Interrupt Enable
This bit is set or reset by software and cleared by
hardware reset. This bit enables or disables the in-
terrupt generation depending on interrupt flag
0: Interrupt not generated
1: Interrupt generated if interrupt flag is set
Note:
This bit should be set to enable interrupt only after
the comparator has been switched ON, i.e. when
CMPON is set.
Once CMPON bit is set, it is recommended to wait
the specified stabilization time before setting
CMPIE bit in order to avoid a spurious interrupt
(see
Bit 2 : CMP Comparator Output
This bit is set or reset by software and cleared by
hardware reset. It stores the value of comparator
output.
Table 21. Analog Comparator Register Map and Reset Values
Address
interrupt if CMPIE is set.
002Ch
002Dh
(Hex.)
section 13.12 on page
VREFCR
Reset Value
CMPCR
Reset value
Register
Label
VCEXT
CHYST
143).
7
0
1
VCBGR
6
0
0
-
CINV
VR3
5
0
0
Bit 1 = COUT Comparator Output Enable on Port
This bit is set or cleared by software. When this bit
is set, the comparator output is available on PA7
port.
0 : Comparator output not connected to PA7
1 : Comparator output connected to PA7
Bit 0 : CMPON Comparator ON/OFF
This bit is set or cleared by software and reset by
hardware reset. This bit is used to switch ON/OFF
the comparator, internal voltage reference and
current bias which provides 4µA current to both.
0: Comparator, Internal Voltage Reference, Bias
1: Comparator, Internal Voltage Reference, Bias
Note: For the comparator interrupt generation, it
takes 250ns delay from comparator output change
to rising or falling edge of interrupt generated.
OFF (in power-down state).
ON
CMPIF
VR2
4
0
0
CMPIE
VR1
3
0
0
CMP
VR0
2
0
0
COUT
ST7LITE1xB
1
0
0
-
CMPON
103/159
0
0
0
-