STM8S105K6B6 STMicroelectronics, STM8S105K6B6 Datasheet - Page 51
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STM8S105K6B6
Manufacturer Part Number
STM8S105K6B6
Description
MCU 8BIT 32K FLASH 32-SDIP
Manufacturer
STMicroelectronics
Series
STM8Sr
Datasheet
1.STM8S105C4T6.pdf
(127 pages)
Specifications of STM8S105K6B6
Core Processor
STM8
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.95 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-SDIP (0.400", 10.16mm)
Processor Series
STM8S10x
Core
STM8
3rd Party Development Tools
EWSTM8
Development Tools By Supplier
STICE-SYS001
For Use With
497-10040 - EVAL KIT STM8S DISCOVERY497-10593 - KIT STARTER FOR STM8S207/8 SER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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STM8S105xx
Addr.
0x480C
0x480D
0x480E
0x487E
0x487F
Option
name
Reserved
Bootloader
Option byte no.
OPT0
OPT1
OPT2
OPT3
Option
byte no.
NOPT6
OPT7
NOPT7
OPTBL
NOPTBL
Option bits
7
Reserved
Reserved
Reserved
BL[7:0]
NBL[7:0]
Description
6
ROP[7:0] Memory readout protection (ROP)
AAh: Enable readout protection (write access via SWIM protocol)
Note: Refer to the family reference manual (RM0016) section on
Flash/EEPROM memory readout protection for details.
UBC[7:0] User boot code area
0x00: no UBC, no write-protection
0x01: Page 0 to 1 defined as UBC, memory write-protected
0x02: Page 0 to 3 defined as UBC, memory write-protected
0x03: Page 0 to 4 defined as UBC, memory write-protected
...
0x3E: Pages 0 to 63 defined as UBC, memory write-protected
Other values: Reserved
Note: Refer to the family reference manual (RM0016) section on
Flash write protection for more details.
AFR[7:0]
Refer to following table for the alternate function remapping
decriptions of bits [7:2].
HSITRIM:High speed internal clock trimming register size
0: 3-bit trimming supported in CLK_HSITRIMR register
1: 4-bit trimming supported in CLK_HSITRIMR register
Table 13: Option byte description
DocID14771 Rev 10
5
4
3
2
1
0
Option bytes
Factory
default
setting
FFh
00h
FFh
00h
FFh
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