Z86E0208HSG1925 Zilog, Z86E0208HSG1925 Datasheet - Page 35

• Manufacturer Part Number: Z86E0208HSG1925
• Description: IC Z8 .5K OTP 8MHZ 20-SSOP
• Manufacturer: Zilog
• Series: Z8®r

Specifications of Z86E0208HSG1925

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: POR, WDT
• Number Of I /o: 14
• Program Memory Size: 512B (512 x 8)
• Program Memory Type: OTP
• Ram Size: 61 x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-SSOP
• Processor Series: Z86E02x
• Core: Z8
• Data Bus Width: 8 bit
• Data Ram Size: 61 B
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 14
• Number Of Timers: 1
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3946; Z86E0208HSG1925

PS014802-0903
Address Register
FFh
FDh
FCh
FBh
FAh
F9h
F8h*
F7h*
F6h*
F3h
F2h
F1h
Note: Registers are not reset after a Stop-Mode Recovery using P27 pin. A subsequent reset causes these control
registers to be reconfigured as indicated in Table 14 and the user must avoid bus contention on the port pins
or it may affect device reliability
SPL
RP
FLAGS
IMR
IRQ
IPR
P01M
P3M
P2M
PRE1
T1
TMR
A timer circuit clocked by a dedicated on-board RC oscillator is used for a POR
timer function. The POR time allows V
before instruction execution begins. The POR timer circuit is a one-shot timer trig-
gered by one of the four following conditions:
•
•
•
•
Watch-Dog Timer Reset
The WDT is a retriggerable one-shot timer that resets the Z8
minal count. The WDT is initially enabled by executing the WDT instruction and is
retriggered on subsequent execution of the WDT instruction. The timer circuit is
driven by an on-board RC oscillator.
Power-bad to power-good status
Stop-Mode Recovery
WDT time-out
WDH time-out (in Halt mode)
Reset Condition
D7 D6 D5 D4 D3 D2 Dl
0
0
U
0
U
U
U
U
1
U
U
0
Table 14. Z8
0
0
U
U
U
U
U
U
1
U
U
0
0
0
U
U
0
U
U
U
1
U
U
0
0
0
U
U
0
U
0
0
1
0
0
0
®
Control Registers Reset Values*
0
0
U
U
0
U
U
U
1
U
U
0
0
0
U
U
0
U
1
U
1
U
U
0
General-Purpose OTP MCU with 14 I/O Lines
0
0
U
U
0
U
0
0
1
0
U
0
D0 Comments
0
0
U
U
0
U
1
0
1
0
U
0
CC
and the oscillator circuit to stabilize
IRQ3 is used for positive edge detection
Inputs after reset
®
if it reaches its ter-
Z86E02 SL 1925
29