ST7FLITES5Y0M6TR STMicroelectronics, ST7FLITES5Y0M6TR Datasheet - Page 51
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ST7FLITES5Y0M6TR
Manufacturer Part Number
ST7FLITES5Y0M6TR
Description
IC MCU 8BIT 1K FLASH 16-SOIC
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST7FLITES2Y0B6.pdf
(124 pages)
Specifications of ST7FLITES5Y0M6TR
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
13
Program Memory Size
1KB (1K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-SOIC (3.9mm Width)
Processor Series
ST7FLITESx
Core
ST7
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
13
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7FLIT0-IND/USB, ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 5 Channel
For Use With
497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5049 - KIT STARTER RAISONANCE ST7FLITE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
LITE TIMER (Cont’d)
Input Capture
The 8-bit input capture register is used to latch the
free-running upcounter after a rising or falling edge
is detected on the LTIC pin. When an input capture
occurs, the ICF bit is set and the LTICR register
contains the value of the free-running upcounter.
An interrupt is generated if the ICIE bit is set. The
ICF bit is cleared by reading the LTICR register.
The LTICR is a read only register and always con-
tains the data from the last input capture. Input
capture is inhibited if the ICF bit is set.
11.1.4 Low Power Modes
Figure 33. Input Capture Timing Diagram
Mode
SLOW
WAIT
ACTIVE HALT
HALT
LTICR REGISTER
8-bit COUNTER
ICF FLAG
LTIC PIN
f
OSC
Description
f
No effect on Lite timer
(this peripheral is driven directly by
f
No effect on Lite timer
No effect on Lite timer
Lite timer stops counting
CPU
/32
OSC
/32)
01h
(@ 8 MHz f
4µs
02h
xxh
OSC
)
03h
04h
11.1.5 Interrupts
Note: The TBF and ICF interrupt events are con-
nected to separate interrupt vectors (see Inter-
rupts chapter).
Timebase and IC events generate an interrupt if
the enable bit is set in the LTCSR register and the
interrupt mask in the CC register is reset (RIM in-
struction).
Timebase
Event
IC Event
05h
Interrupt
Event
04h
06h
Event
Flag
TBF
ICF
ST7LITE0xY0, ST7LITESxY0
07h
Control
Enable
TBIE
ICIE
Bit
LTIC REGISTER
07h
from
Wait
CLEARED
Exit
READING
Yes
BY S/W
from
Exit
Halt
No
t
Active-
from
Exit
Halt
Yes
51/124
No
1