EP9312-IB Cirrus Logic Inc, EP9312-IB Datasheet - Page 8

• Manufacturer Part Number: EP9312-IB
• Description: IC ARM920T MCU 200MHZ 352-PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-IB

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 352-BGA
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1259

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Description 1
Under certain circumstances, data in coprocessor registers or in memory may be corrupted. The following
sequence of instructions will cause the corruption:
1) Let the first instruction be both:
2) Let the second instruction be any two-word coprocessor load or store
If the second instruction is a load, the upper word in the target register will generally get an incorrect value.
If the second instruction is a store, the word immediately following the second target memory location will
be written; that is, instead of just writing two consecutive 32-bit words (a 64-bit value or a double value) to
memory, a third 32-bit word immediately following this will be written, leading to memory corruption.
Consider a simple example with a store instruction:
Three words will be written to memory. The correct values will appear at the memory location pointed to by
r2, and r2 + 0x4. Another value will be written at r2 + 0x8.
Consider now an example with a load instruction:
The final value in c3 will be incorrect. The lower 32 bits will be correct, while the upper 32 bits will be
incorrect.
Finally, consider a case where a branch occurs:
Note: The above examples assume that the cfaddne or cfadd would busy-wait (for whatever reason) if
actually executed. If not, the execution of the following instruction would be correct.
cfaddne
cfstr64
cfaddne
cfldrd
target
cfldrd
b
nop
cfadd
- any coprocessor instruction that is not executed
- stalled by the coprocessor due to an internal dependency.
c0, c1, c2
c3, [r2, #0x0]
c0, c1, c2
c3, [r2, #0x0]
c3, [r2, #0x0]
target
c0, c1, c2
; assume this does not execute
; assume this does not execute
; though in pipeline, this does not execute
(Continued)
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