ADUC812BSZ Analog Devices Inc, ADUC812BSZ Datasheet - Page 32

IC ADC 12BIT MULTICH MCU 52-MQFP

ADUC812BSZ

Manufacturer Part Number
ADUC812BSZ
Description
IC ADC 12BIT MULTICH MCU 52-MQFP
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC8xxr
Datasheet

Specifications of ADUC812BSZ

Core Size
8-Bit
Program Memory Size
8KB (8K x 8)
Core Processor
8052
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
PSM, Temp Sensor, WDT
Number Of I /o
34
Program Memory Type
FLASH
Eeprom Size
640 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-MQFP, 52-PQFP
Controller Family/series
(8051) 8052
No. Of I/o's
32
Eeprom Memory Size
8KB
Ram Memory Size
256Byte
Cpu Speed
1.3MIPS
No. Of Timers
3
Package
52MQFP
Device Core
8052
Family Name
ADuC8xx
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
32
Interface Type
I2C/SPI/TWI/UART
On-chip Adc
8-chx12-bit
On-chip Dac
2-chx12-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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ADuC812
TIMER/COUNTERS 0 AND 1 OPERATING MODES
The following paragraphs describe the operating modes for
Timer/Counters 0 and 1. Unless otherwise noted, it should be
assumed that these modes of operation are the same for Timer 0
as for Timer 1.
Mode 0 (13-Bit Timer/Counter)
Mode 0 configures an 8-bit timer/counter with a divide-by-32
prescaler. Figure 26 shows Mode 0 operation.
In this mode, the timer register is configured as a 13-bit register. As
the count rolls over from all 1s to all 0s, it sets the timer overflow
flag TF0. The overflow flag, TF0, can then be used to request
an interrupt. The counted input is enabled to the timer when
TR0 = 1 and either Gate = 0 or INT0 = 1. Setting Gate = 1 allows
the timer to be controlled by external input INT0 to facilitate
pulsewidth measurements. TR0 is a control bit in the special
function register TCON; Gate is in TMOD. The 13-bit register
consists of all eight bits of TH0 and the lower five bits of TL0.
The upper three bits of TL0 are indeterminate and should be
ignored. Setting the run flag (TR0) does not clear the registers.
Mode 1 (16-Bit Timer/Counter)
Mode 1 is the same as Mode 0, except that the timer register is
running with all 16 bits. Mode 1 is shown in Figure 27.
P3.2/INT0
P3.2/INT0
P3.4/T0
CORE
P3.4/T0
CORE
CLK
CLK
GATE
GATE
12
Figure 26. Timer/Counter 0, Mode 0
Figure 27. Timer/Counter 0, Mode 1
12
TR0
TR0
C/T = 0
C/T = 1
C/T = 0
C/T = 1
CONTROL
CONTROL
(8 BITS)
(5 BITS)
TL0
TL0
(8 BITS)
(8 BITS)
TH0
TH0
TF0
TF0
INTERRUPT
INTERRUPT
–32–
Mode 2 (8-Bit Timer/Counter with Auto Reload)
Mode 2 configures the timer register as an 8-bit counter (TL0)
with automatic reload, as shown in Figure 28. Overflow from TL0
not only sets TF0, but also reloads TL0 with the contents of TH0,
which is preset by software. The reload leaves TH0 unchanged.
Mode 3 (Two 8-Bit Timer/Counters)
Mode 3 has different effects on Timer 0 and Timer 1. Timer 1 in
Mode 3 simply holds its count. The effect is the same as setting
TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two
separate counters. This configuration is shown in Figure 29.
TL0 uses the Timer 0 control bits: C/T, Gate, TR0, INT0, and
TF0. TH0 is locked into a timer function (counting machine
cycles) and takes over the use of TR1 and TF1 from Timer 1.
Thus, TH0 now controls the Timer 1 interrupt. Mode 3 is
provided for applications requiring an extra 8-bit timer or counter.
When Timer 0 is in Mode 3, Timer 1 can be turned on and off by
switching it out of, and into, its own Mode 3, or can still be used
by the serial interface as a baud rate generator. In fact, it can be used
in any application not requiring an interrupt from Timer 1 itself.
P3.2/INT0
P3.4/T0
P3.2/INT0
CORE
GATE
CLK
P3.4/T0
CLK/12
CORE
CORE
GATE
CLK
TR1
Figure 28. Timer/Counter 0, Mode 2
Figure 29. Timer/Counter 0, Mode 3
12
12
TR0
TR0
C/T = 0
C/T = 1
C/T = 0
C/T = 1
CLK/12
CORE
CONTROL
CONTROL
CONTROL
RELOAD
(8 BITS)
(8 BITS)
(8 BITS)
(8 BITS)
TH0
TL0
TH0
TL0
TF0
TF1
TF0
INTERRUPT
INTERRUPT
INTERRUPT
REV. E

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