P80C32SBPN,112 NXP Semiconductors, P80C32SBPN,112 Datasheet - Page 25

• Manufacturer Part Number: P80C32SBPN,112
• Description: IC 80C51 MCU 256X8 ROMLESS 40DIP
• Manufacturer: NXP Semiconductors
• Series: 80Cr

Specifications of P80C32SBPN,112

• Program Memory Type: ROMless
• Package / Case: 40-DIP (0.600", 15.24mm)
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: UART/USART
• Peripherals: POR
• Number Of I /o: 32
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Processor Series: P80C3x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: 0 C
• Program Memory Size: 32 KB
• Package: 40PDIP
• Device Core: 80C51
• Family Name: 80C
• Maximum Speed: 16 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-1005-5; 935255880112; P80C32SBPN

Philips Semiconductors
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The first character is always
‘t’ (= time). The other characters, depending on their positions,
indicate the name of a signal or the logical status of that signal. The
designations are:
A – Address
C – Clock
D – Input data
H – Logic level high
I – Instruction (program memory contents)
L – Logic level low, or ALE
2000 Aug 07
PORT 0
PORT 2
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
PSEN
ALE
RD
PORT 0
PORT 2
PSEN
ALE
t
AVLL
FROM RI OR DPL
A0–A7
t
LLAX
t
t
AVWL
LHLL
t
t
LLWL
AVLL
A0–A7
Figure 14. External Program Memory Read Cycle
t
t
AVDV
P2.0–P2.7 OR A8–A15 FROM DPF
RLAZ
Figure 15. External Data Memory Read Cycle
t
LLDV
t
t
t
AVIV
LLAX
LLPL
t
LLIV
t
t
PLIV
RLDV
A0–A15
t
PLAZ
t
PLPH
t
RLRH
t
PXIX
INSTR IN
25
t
RHDX
DATA IN
P – PSEN
Q – Output data
R – RD signal
t – Time
V – Valid
W – WR signal
X – No longer a valid logic level
Z – Float
Examples: t
t
PXIZ
t
RHDZ
t
t
AVLL
WHLH
LLPL
= Time for address valid to ALE low.
=Time for ALE low to PSEN low.
A0–A7
A0–A7 FROM PCL
A0–A15 FROM PCH
A8–A15
80C31/80C32
Product specification
SU00006
INSTR IN
SU00025