P87C51X2BBD,157 NXP Semiconductors, P87C51X2BBD,157 Datasheet - Page 32
![IC 80C51 MCU 128 RAM 44LQFP](/photos/12/13/121370/44-lqfp_sml.jpg)
P87C51X2BBD,157
Manufacturer Part Number
P87C51X2BBD,157
Description
IC 80C51 MCU 128 RAM 44LQFP
Manufacturer
NXP Semiconductors
Series
87Cr
Datasheet
1.P87C52X2BN112.pdf
(62 pages)
Specifications of P87C51X2BBD,157
Program Memory Type
OTP
Program Memory Size
4KB (4K x 8)
Package / Case
44-LQFP
Core Processor
8051
Core Size
8-Bit
Speed
33MHz
Connectivity
EBI/EMI, UART/USART
Peripherals
POR
Number Of I /o
32
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Processor Series
P87C5x
Core
80C51
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
UART
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
OM10064 - EMULATOR 80C51 PDS51-MK2
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
935271374157
P87C51X2BBD
P87C51X2BBD
P87C51X2BBD
P87C51X2BBD
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
P87C51X2BBD,157
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips Semiconductors
2003 Jan 24
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V),
low power, high speed (30/33 MHz)
Figure 20. UART Multiprocessor Communication, Automatic Address Recognition
START
BIT
IN UART MODE 2 OR MODE 3 AND SM2 = 1:
– WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES
– WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS.
D0
SM0 / FE
INTERRUPT IF REN=1, RB8=1 AND “RECEIVED ADDRESS” = “PROGRAMMED ADDRESS”
RECEIVED ADDRESS D0 TO D7
SMOD1
PROGRAMMED ADDRESS
D0
0 : SCON.7 = SM0
1 : SCON.7 = FE
D1
SMOD0
SM1
D1
Figure 19. UART Framing Error Detection
D2
SM2
SM0
D2
–
1
1
D3
REN
SM1
D3
POF
DATA BYTE
1
0
SET FE BIT IF STOP BIT IS 0 (FRAMING ERROR)
SM0 TO UART MODE CONTROL
D4
32
TB8
D4
SM2
GF1
COMPARATOR
D5
1
D5
RB8
GF0
REN
1
D6
D6
PD
TB8
TI
D7
X
D7
P80C3xX2; P80C5xX2;
RB8
IDL
D8
RI
MODE 2, 3
ONLY IN
D8
SCON
(98H)
PCON
(87H)
TI
STOP
BIT
SU01191
RI
P87C5xX2
SU00045
SCON
(98H)
Product data