AT91SAM9263B-CU Atmel, AT91SAM9263B-CU Datasheet - Page 18

• Manufacturer Part Number: AT91SAM9263B-CU
• Description: IC ARM9 MCU 200 MHZ 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9263B-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: CAN, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: 2-Wire, EBI, I2S, MCI, SPI, USART
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9263-EK
• Minimum Operating Temperature: - 40 C
• Package: 324TFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 200 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 160
• Ram Memory Size: 96KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• For Use With: AT91SAM9263-EK - KIT EVAL FOR AT91SAM9263AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q3735625

7.5
Table 7-3.
7.6
18
0
1
2
3
4
5
6
Internal 80 Kbyte
Internal 16 Kbyte
Peripheral Bridge
DMA Controller
USB Host User
Master to Slave Access
LCD Controller
Peripheral DMA Controller
User Interface
User Interface
Internal ROM
External Bus
External Bus
Master
SRAM Bank
AT91SAM9263 Preliminary
Slave
Interface 0
Interface 1
Interface
SRAM
Masters to Slaves Access
In most cases, all the masters can access all the slaves. However, some paths do not make
sense, for example, allowing access from the Ethernet MAC to the Internal Peripherals. Thus,
these paths are forbidden or simply not wired, and are shown as “-” in
The Peripheral DMA Controller handles transfer requests from the channel according to the fol-
lowing priorities (low to high priorities):
OHCI USB
Controller
• Acts as one Matrix Master
• Allows data transfers between a peripheral and memory without any intervention of the
• Next Pointer support, removes heavy real-time constraints on buffer management.
• Twenty channels
Host
processor
X
X
X
X
X
0
-
-
-
-
– Two for each USART
– Two for the Debug Unit
– Two for each Serial Synchronous Controller
– Two for each Serial Peripheral Interface
– Two for the AC97 Controller
– One for each Multimedia Card Interface
– DBGU Transmit Channel
– USART2 Transmit Channel
Interface
Sensor
Image
X
X
X
X
X
1
-
-
-
-
Controller
Graphics
Two D
X
X
X
X
X
2
-
-
-
-
Controller
DMA
X
X
X
X
X
X
3
-
-
-
Ethernet
MAC
X
X
X
X
X
4
-
-
-
-
Controller
LCD
5
X
X
X
X
X
-
-
-
-
Table
Peripheral
Controller
DMA
X
X
X
X
X
X
6249HS–ATARM–27-Jul-09
6
-
-
-
7-3.
Instruction
ARM926
Data &
7&8
X
X
X
X
X
X
X
X
X