ATSAM3U4EA-AU Atmel, ATSAM3U4EA-AU Datasheet - Page 25

• Manufacturer Part Number: ATSAM3U4EA-AU
• Description: IC MCU 32BIT 256KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4EA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b, 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 4xUSART, 2xTWI, 5xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, AT91SAM3U-EK, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Controller Family/series: SAM3U
• No. Of I/o's: 96
• Ram Memory Size: 52KB
• Cpu Speed: 96MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.4
6.5
6.6
6.7
6430DS–ATARM–28-Mar-11
Test Pin
NRST Pin
NRSTB Pin
ERASE Pin
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It
integrates a permanent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left uncon-
nected for normal operations.
By default, the JTAG Debug Port is active. If the debugger host wants to switch to the Serial
Wire Debug Port, it must provide a dedicated JTAG sequence on TMS/SWDIO and
TCK/SWCLK which disables the JTAG-DP and enables the SW-DP. When the Serial Wire
Debug Port is active, TDO/TRACESWO can be used for trace.
The asynchronous TRACE output (TRACESWO) is multiplexed with TDO. So the asynchronous
trace can only be used with SW-DP, not JTAG-DP.
All the JTAG signals are supplied with VDDIO except JTAGSEL, supplied by VDDBU.
The TST pin is used for JTAG Boundary Scan Manufacturing Test or fast flash programming
mode of the SAM3U series. The TST pin integrates a permanent pull-down resistor of about 15
kΩ to GND, so that it can be left unconnected for normal operations. To enter fast programming
mode, see the “Fast Flash Programming Interface” section of the product datasheet. For more
on the manufacturing and test mode, refer to the “Debug and Test” section of the product
datasheet.
The NRST pin is bidirectional. It is handled by the on-chip reset controller and can be driven low
to provide a reset signal to the external components or asserted low externally to reset the
microcontroller. It will reset the Core and the peripherals, except the Backup region (RTC, RTT
and Supply Controller). There is no constraint on the length of the reset pulse and the reset con-
troller can guarantee a minimum pulse length.
The NRST pin integrates a permanent pull-up resistor to VDDIO of about 100 kΩ.
The NRSTB pin is input only and enables asynchronous reset of the SAM3U when asserted low.
The NRSTB pin integrates a permanent pull-up resistor of about 15 kΩ. This allows connection
of a simple push button on the NRSTB pin as a system-user reset. In all modes, this pin will
reset the chip including the Backup region (RTC, RTT and Supply Controller). It reacts as the
Power-on reset. It can be used as an external system reset source. In harsh environments, it is
recommended to add an external capacitor (10 nF) between NRSTB and VDDBU. (For filtering
values refer to “I/O Characteristics” in the “Electrical Characteristics” section of the product
datasheet.)
It embeds an anti-glitch filter.
The ERASE pin is used to reinitialize the Flash content and some of its NVM bits. It integrates a
permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for nor-
mal operations.
This pin is debounced by SCLK to improve the glitch tolerance. When the ERASE pin is tied high
during less than 100 ms, it is not taken into account. The pin must be tied high during more than
220 ms to perform the reinitialization of the Flash.
SAM3U Series
25