AT91SAM9260B-QU Atmel, AT91SAM9260B-QU Datasheet
AT91SAM9260B-QU
Specifications of AT91SAM9260B-QU
Available stocks
Related parts for AT91SAM9260B-QU
AT91SAM9260B-QU Summary of contents
Page 1
Features ® • 180 MHz ARM926EJ-S™ ARM Thumb – 8 KBytes Data Cache, 8 KBytes Instruction Cache, MMU • Memories – 32-bit External Bus Interface supporting 4-bank SDRAM/LPSDR, Static Memories, CompactFlash, SLC NAND Flash with ECC – Two 4-kbyte internal ...
Page 2
Description The AT91SAM9260 is based on the integration of an ARM926EJ-S processor with fast ROM and RAM memories and a wide range of peripherals. The AT91SAM9260 embeds an Ethernet MAC, one USB Device Port, and a USB Host control- ...
Page 3
Figure 2-1. AT91SAM9260 Block Diagram 6221I–ATARM–17-Jul-09 Filter AT91SAM9260 3 ...
Page 4
Signal Description Table 3-1. Signal Description List Signal Name Function VDDIOM EBI I/O Lines Power Supply VDDIOP0 Peripherals I/O Lines Power Supply VDDIOP1 Peripherals I/O Lines Power Supply VDDBU Backup I/O Lines Power Supply VDDANA Analog Power Supply VDDPLL ...
Page 5
Table 3-1. Signal Description List (Continued) Signal Name Function NRST Microcontroller Reset TST Test Mode Select BMS Boot Mode Select DRXD Debug Receive Data DTXD Debug Transmit Data IRQ0 - IRQ2 External Interrupt Inputs FIQ Fast Interrupt Input PA0 - ...
Page 6
Table 3-1. Signal Description List (Continued) Signal Name Function NANDCS NAND Flash Chip Select NANDOE NAND Flash Output Enable NANDWE NAND Flash Write Enable NANDALE NAND Flash Address Latch Enable NANDCLE NAND Flash Command Latch Enable SDCK SDRAM Clock SDCKE ...
Page 7
Table 3-1. Signal Description List (Continued) Signal Name Function TCLKx TC Channel x External Clock Input TIOAx TC Channel x I/O Line A TIOBx TC Channel x I/O Line B SPIx_MISO Master In Slave Out SPIx_MOSI Master Out Slave In ...
Page 8
Table 3-1. Signal Description List (Continued) Signal Name Function ISI_D0-ISI_D11 Image Sensor Data ISI_MCK Image Sensor Reference Clock ISI_HSYNC Image Sensor Horizontal Synchro ISI_VSYNC Image Sensor Vertical Synchro ISI_PCK Image Sensor Data clock AD0-AD3 Analog Inputs ADVREF Analog Positive Reference ...
Page 9
Package and Pinout The AT91SAM9260 is available in two packages: • 208-pin PQFP Green package (0.5mm pitch) • 217-ball LFBGA Green package (0.8 mm ball pitch) 4.1 208-pin PQFP Package Outline Figure 4-1 A detailed mechanical description is given ...
Page 10
PQFP Pinout Table 4-1. Pinout for 208-pin PQFP Package Pin Signal Name Pin 1 PA24 53 2 PA25 54 3 PA26 55 4 PA27 56 5 VDDIOP0 57 6 GND 58 7 PA28 59 8 PA29 60 9 ...
Page 11
Table 4-1. Pinout for 208-pin PQFP Package (Continued) Pin Signal Name Pin 49 SHDN 101 50 HDMA 102 51 HDPA 103 52 VDDIOP0 104 4.3 217-ball LFBGA Package Outline Figure 4-2 A detailed mechanical description is given in the section ...
Page 12
LFBGA Pinout Table 4-2. Pinout for 217-ball LFBGA Package Pin Signal Name Pin A1 CFIOW/NBS3/NWR3 D5 A2 NBS0/ NWR2/NBS2/ A11 D10 A7 A13 D11 A8 BA0/A16 D12 A9 ...
Page 13
Table 4-2. Pinout for 217-ball LFBGA Package (Continued) Pin Signal Name C16 VDDIOP0 C17 SHDN RAS Power Considerations 5.1 Power Supplies The AT91SAM9260 has several types of power supply pins: • VDDCORE ...
Page 14
Programmable I/O Lines Power Supplies The power supplies pins VDDIOM accept two voltage ranges. This allows the device to reach its maximum speed either out of 1.8V or 3.3V external memories. The target maximum speed is 100 MHz on ...
Page 15
PIO Controllers All the I/O lines managed by the PIO Controllers integrate a programmable pull-up resistor. Refer to the section on DC Characteristics in “AT91SAM9260 Electrical Characteristics” for more information. Programming of this pull-up resistor is performed independently for ...
Page 16
Memories Figure 7-1. AT91SAM9260 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 256M Bytes 0x0FFF FFFF 0x1000 0000 EBI 256M Bytes Chip Select 0 0x1FFF FFFF 0x2000 0000 EBI 256M Bytes Chip Select 1/ SDRAMC 0x2FFF FFFF 0x3000 ...
Page 17
A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the Advanced High Performance Bus (AHB) for its Master and Slave interfaces with additional features. Decoding breaks up the 4G bytes of address space ...
Page 18
The AT91SAM9260 matrix manages a boot memory that depends on the level on the BMS pin at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved for this purpose. If BMS is detected at 1, ...
Page 19
ECC Controller • Additional logic for NAND Flash • Full 32-bit External Data Bus • 26-bit Address Bus (up to 64MBytes linear) • chip selects, Configurable Assignment: – Static Memory Controller on NCS0 – ...
Page 20
Error detection – Refresh Error Interrupt • SDRAM Power-up Initialization by software • CAS Latency and 3 supported • Auto Precharge Command not used 7.2.4 Error Corrected Code Controller • Tracking the accesses to a NAND ...
Page 21
System Controller The System Controller is a set of peripherals that allows handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc. The System Controller User Interface also embeds the registers that configure ...
Page 22
Block Diagram Figure 8-1. AT91SAM9260 System Controller Block Diagram irq0-irq2 periph_irq[2..24] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset dbgu_rxd periph_nreset proc_nreset NRST VDDCORE POR VDDBU VDDBU POR backup_nreset SHDN WKUP RC OSC OSC_SEL SLOW XIN32 CLOCK OSC XOUT32 XIN ...
Page 23
Power Management Controller • Provides: – the Processor Clock PCK – the Master Clock MCK, in particular to the Matrix and the memory interfaces – the USB Device Clock UDPCK – independent peripheral clocks, typically at the frequency of ...
Page 24
Backup Section The AT91SAM9260 features a Backup Section that embeds: • RC Oscillator • Slow Clock Oscillator • SCKR register • RTT • Shutdown Controller • 4 backup registers • A part of RSTC This section is powered by ...
Page 25
Table 9-1. Peripheral Note: Setting AIC, SYSC, UHP and IRQ0-2 bits in the clock set/clear registers of the PMC has no effect. 9.2.1 Peripheral Interrupts ...
Page 26
Note that some peripheral functions which are output only might be duplicated ...
Page 27
PIO Controller A Multiplexing Table 9-2. Multiplexing on PIO Controller A PIO Controller A I/O Line Peripheral A PA0 SPI0_MISO PA1 SPI0_MOSI PA2 SPI0_SPCK PA3 SPI0_NPCS0 PA4 RTS2 PA5 CTS2 PA6 MCDA0 PA7 MCCDA PA8 MCCK PA9 MCDA1 PA10 ...
Page 28
PIO Controller B Multiplexing Table 9-3. Multiplexing on PIO Controller B PIO Controller B I/O Line Peripheral A Peripheral B PB0 SPI1_MISO TIOA3 PB1 SPI1_MOSI TIOB3 PB2 SPI1_SPCK TIOA4 PB3 SPI1_NPCS0 TIOA5 PB4 TXD0 PB5 RXD0 PB6 TXD1 TCLK1 ...
Page 29
PIO Controller C Multiplexing Table 9-4. Multiplexing on PIO Controller C PIO Controller C I/O Line Peripheral A PC0 PC1 (1) PC2 (1) PC3 PC4 A23 PC5 A24 PC6 TIOB2 PC7 TIOB1 PC8 NCS4/CFCS0 PC9 NCS5/CFCS1 PC10 A25/CFRNW PC11 ...
Page 30
AT91SAM9260 30 6221I–ATARM–17-Jul-09 ...
Page 31
ARM926EJ-S Processor Overview 10.1 Description The ARM926EJ-S processor is a member of the ARM9 sors. The ARM926EJ-S implements ARM architecture version 5TEJ and is targeted at multi- tasking applications where full memory management, high performance, low die size and ...
Page 32
Software Control Drain • Standard ARM v4 and v5 Memory Management Unit (MMU) – Access Permission for Sections – Access Permission for large pages and small pages can be specified separately for each quarter of the page – 16 ...
Page 33
Block Diagram Figure 10-1. ARM926EJ-S Internal Functional Block Diagram ETM Interface WDATA RDATA ARM9EJ-S EmbeddedICE Processor -RT INSTR ICE Interface 10.4 ARM9EJ-S Processor 10.4.1 ARM9EJ-S Operating States The ARM9EJ-S processor can operate in three different states, each with a ...
Page 34
ARM state and Jazelle state using the BXJ instruction All exceptions are entered, handled and exited in ARM state exception occurs in Thumb or Jazelle states, the processor reverts to ARM state. The transition back to Thumb ...
Page 35
Supervisor mode is a protected mode for the operating system • Abort mode is entered after a data or instruction prefetch abort • System mode is a privileged user mode for the operating system • Undefined mode is entered ...
Page 36
The ARM state register set contains 16 directly-accessible registers r15, and an additional register, the Current Program Status Register (CPSR). Registers r0 to r13 are general-purpose registers used to hold either data or address values. Register r14 is ...
Page 37
Figure 10-2. Status Register Format Figure 10-2 • N: Negative, Z: Zero, C: Carry, and V: Overflow are the four ALU flags • The Sticky Overflow (Q) flag can be set by certain multiply and fractional arithmetic instructions like QADD, ...
Page 38
The BKPT, or Undefined instruction, and SWI exceptions are mutually exclusive. There is one exception in the priority scheme though, when FIQs are enabled and a Data Abort occurs at the same time as an FIQ, the ARM9EJ-S core enters ...
Page 39
Data processing instructions • Status register transfer instructions • Load and Store instructions • Coprocessor instructions • Exception-generating instructions ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition code field (bits[31:28]). Table 10-2 Table 10-2. Mnemonic ...
Page 40
New ARM Instruction Set Table 10-3. Mnemonic BXJ BLX SMLAxy SMLAL SMLAWy SMULxy SMULWy QADD QDADD QSUB QDSUB Notes: 10.4.10 Thumb Instruction Set Overview The Thumb instruction set is a re-encoded subset of the ARM instruction set. The Thumb ...
Page 41
Table 10-4. Mnemonic LSL ASR MUL B BX LDR LDRH LDRB LDRSH LDMIA PUSH BCC 10.5 CP15 Coprocessor Coprocessor 15, or System Control Coprocessor CP15, is used to configure and control all the items in the list below: • ARM9EJ-S ...
Page 42
Table 10-5. Register Notes: 10.5.1 CP15 Registers Access CP15 registers can only be accessed in privileged mode by: • MCR (Move to Coprocessor from ARM Register) instruction is used to write an ARM register to CP15. • MRC (Move to ...
Page 43
The assembler code for these instructions is: The MCR, MRC instructions bit pattern is shown below cond 23 22 opcode_1 opcode_2 • CRm[3:0]: Specified Coprocessor Action Determines specific coprocessor action. Its value is ...
Page 44
Memory Management Unit (MMU) The ARM926EJ-S processor implements an enhanced ARM architecture v5 MMU to provide vir- tual memory features required by operating systems like Symbian OS Linux. These virtual memory features are memory access permission controls and virtual ...
Page 45
Translation Look-aside Buffer (TLB) The Translation Look-aside Buffer (TLB) caches translated entries and thus avoids going through the translation process every time. When the TLB contains an entry for the MVA (Modi- fied Virtual Address), the access control logic ...
Page 46
A new feature is now supported by ARM926EJ-S caches called allocate on read-miss commonly known as wrapping. This feature enables the caches to perform critical word first cache refilling. This means that when a request for a word causes a ...
Page 47
The DCache contains an eight data word entry, single address entry write-back buffer used to hold write-back data for cache line eviction or cleaning of dirty cache lines. The Write Buffer can hold words of data and ...
Page 48
... Note that the Atmel bus is AHB-Lite protocol compliant, hence it does not support split and retry requests. Table 10-7 are used for. Table 10-7. Supported Transfers HBurst[2:0] Description SINGLE Single transfer INCR4 Four-word incrementing burst INCR8 Eight-word incrementing burst ...
Page 49
AT91SAM9260 Debug and Test 11.1 Description The AT91SAM9260 features a number of complementary debug and test capabilities. A com- mon JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. The ...
Page 50
Block Diagram Figure 11-1. Debug and Test Block Diagram Boundary Port ARM9EJ-S ARM926EJ-S PDC TAP: Test Access Port AT91SAM9260 50 ICE/JTAG TAP Reset and Test ICE-RT DBGU TMS TCK TDI NTRST JTAGSEL TDO RTCK POR TST DTXD DRXD 6221I–ATARM–17-Jul-09 ...
Page 51
Application Examples 11.4.1 Debug Environment Figure 11-2 on page 51 face is used for standard debugging functions, such as downloading code and single-stepping through the program. A software debugger running on a personal computer provides the user interface for ...
Page 52
Test Environment Figure 11-3 on page 52 preted by the tester. In this example, the “board in test” is designed using a number of JTAG- compliant devices. These devices can be connected to form a single scan chain. Figure ...
Page 53
... JTAG registers) and propagates them to the next chip in the serial test circuit. NTRST (optional in IEEE Standard 1149. Test-ReSeT input which is mandatory in ARM cores and used to reset the debug logic. On Atmel ARM926EJ-S-based cores, NTRST is a Power On Reset output asserted on power on. If necessary, the user can also reset the debug logic with the NTRST pin assertion during 2 ...
Page 54
Debug Unit The Debug Unit provides a two-pin (DXRD and TXRD) USART that can be used for several debug and trace purposes and offers an ideal means for in-situ programming solutions and debug monitor communication. Moreover, the association with ...
Page 55
Table 11-2. 6221I–ATARM–17-Jul-09 AT91SAM9260 JTAG Boundary Scan Register 297 A13 296 295 A14 294 293 A15 292 291 A16 290 289 A17 288 287 A18 286 285 A19 284 283 A2 282 281 A20 280 279 A21 278 277 A22 ...
Page 56
Table 11-2. 260 259 258 257 256 255 254 253 252 251 250 249 248 247 246 245 244 243 242 241 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 AT91SAM9260 56 ...
Page 57
Table 11-2. 6221I–ATARM–17-Jul-09 AT91SAM9260 JTAG Boundary Scan Register 224 NANDWE 223 222 NCS0 221 220 NCS1 219 218 NRD 217 216 NRST 215 214 NWR0 213 212 NWR1 211 210 NWR3 209 208 OSCSEL 207 PA0 206 205 PA1 204 ...
Page 58
Table 11-2. 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 AT91SAM9260 58 ...
Page 59
Table 11-2. 6221I–ATARM–17-Jul-09 AT91SAM9260 JTAG Boundary Scan Register 151 PA6 150 149 PA7 148 147 PA8 146 145 PA9 144 143 PB0 142 141 PB1 140 139 PB10 138 137 PB11 136 135 134 133 132 131 PB14 130 129 ...
Page 60
Table 11-2. 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 AT91SAM9260 60 AT91SAM9260 JTAG Boundary Scan Register PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 99 PB29 98 97 PB3 96 95 ...
Page 61
Table 11-2. 6221I–ATARM–17-Jul-09 AT91SAM9260 JTAG Boundary Scan Register 79 PC0 78 77 PC1 76 75 PC10 74 73 PC11 PC13 68 67 PC14 66 65 PC15 64 63 PC16 62 61 PC17 60 59 PC18 58 ...
Page 62
Table 11-2. AT91SAM9260 62 AT91SAM9260 JTAG Boundary Scan Register 43 PC25 42 41 PC26 40 39 PC27 38 37 PC28 36 35 PC29 PC30 30 29 PC31 28 27 PC4 26 25 PC5 24 23 PC6 ...
Page 63
Table 11-2. 6221I–ATARM–17-Jul-09 AT91SAM9260 JTAG Boundary Scan Register 07 SDCKE 06 05 SDWE 04 03 SHDN 02 01 TST 00 WKUP AT91SAM9260 CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL OUT OUTPUT INPUT INPUT INPUT INPUT 63 ...
Page 64
JID Code Register Access: Read-only 31 30 VERSION PART NUMBER 7 6 • VERSION[31:28]: Product Version Number Set to 0x0. • PART NUMBER[27:12]: Product Part Number Product part Number is 0x5B13 • MANUFACTURER IDENTITY[11:1] Set ...
Page 65
Reset Controller (RSTC) 12.1 Description The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the sys- tem without any external components. It reports which reset occurred last. The Reset Controller also drives independently or ...
Page 66
Processor reset line. It also resets the Watchdog Timer. • backup_nreset: Affects all the peripherals powered by VDDBU. • periph_nreset: Affects the whole set of embedded peripherals. • nrst_out: Drives the NRST pin. These reset signals are asserted ...
Page 67
NRST External Reset Control The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the “nrst_out” signal is driven low by the NRST Manager for a time programmed by the field ERSTL in ...
Page 68
When VDDBU is detected low by the Backup Supply POR Cell, all resets signals are immedi- ately asserted, even if the Main Supply POR Cell does not report a Main Supply shutdown. VDDBU only activates the backup_nreset signal. The backup_nreset ...
Page 69
Wake-up Reset The Wake-up Reset occurs when the Main Supply is down. When the Main Supply POR output is active, all the reset signals are asserted except backup_nreset. When the Main Supply pow- ers up, the POR output is ...
Page 70
When the processor reset signal is released, the RSTTYP field of the Status Register (RSTC_SR) is loaded with the value 0x4, indicating a User Reset EXTERNAL_RESET_LENGTH Slow Clock cycles, as programmed in the ...
Page 71
The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master Clock (MCK). They are released when the software reset is left, i.e.; syn- chronously to SLCK. If EXTRST is set, ...
Page 72
If WDRPROC = 1, only the processor reset is asserted. The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a processor reset if WDRSTEN is set, the Watchdog Timer is always reset after ...
Page 73
When in Watchdog Reset: – The processor reset is active and so a Software Reset cannot be programmed. – A User Reset cannot be entered. 12.4.6 Reset Controller Status Register The Reset Controller status register (RSTC_SR) provides several status ...
Page 74
Reset Controller (RSTC) User Interface Table 12-1. Register Mapping Offset Register 0x00 Control Register 0x04 Status Register 0x08 Mode Register Note: 1. The reset value of RSTC_SR either reports a General Reset or a Wake-up Reset depending on last ...
Page 75
Reset Controller Control Register Name: RSTC_CR Access Type: Write-only – – – – – – • PROCRST: Processor Reset effect KEY is correct, resets the ...
Page 76
Reset Controller Status Register Name: RSTC_SR Access Type: Read-only 31 30 – – – – – – – – • URSTS: User Reset Status high-to-low edge on NRST happened since ...
Page 77
Reset Controller Mode Register Name: RSTC_MR Access Type: Read-write – – – – – – • URSTEN: User Reset Enable 0 = The detection of a low level on the pin ...
Page 78
AT91SAM9260 78 6221I–ATARM–17-Jul-09 ...
Page 79
AT91SAM9260 Boot Program 13.1 Description The Boot Program integrates different programs permitting download and/or upload into the dif- ferent memories of the product. First, it initializes the Debug Unit serial port (DBGU) and the USB Device Port. Then the ...
Page 80
Figure 13-1. Boot Program Algorithm Flow Diagram Start Internal RC Oscillator No Large Crystal Table SPI DataFlash Boot No SPI DataFlash Boot No NAND Flash Boot No USB Enumeration Run SAM-BA Monitor AT91SAM9260 80 Yes Main Oscillator Bypass No Reduced ...
Page 81
Device Initialization Initialization follows the steps described below: 1. FIQ Initialization 2. Stack setup for ARM supervisor mode 3. External Clock Detection 4. Switch Master Clock on Main Oscillator 5. C variable initialization 6. Main oscillator frequency detection if ...
Page 82
If an external 32768 Hz Oscillator is used (OSCSEL = 1) and Main Oscillator is Table 13-4. 3.0 4.433619 6.144 7.864320 12.0 16.0 24 40.0 Note: 8. Initialization of the DBGU serial port (115200 bauds only ...
Page 83
Figure 13-2. Clocks and DBGU Configurations No Scan Large Crystal Table or Input Frequencies Supported (OSCEL =1 MCK = PLLB/2 UDPCK = PLLB/2 "ROMBoot>" displayed on DBGU DataFlash Boot ? NANDFlash Boot ? No End 6221I–ATARM–17-Jul-09 Start Yes Internal RC ...
Page 84
Figure 13-3. Remap Action after Download Completion 13.4 DataFlash Boot The DataFlash Boot program searches for a valid application in the SPI DataFlash memory valid application is found, this application is loaded into internal SRAM and executed by ...
Page 85
... Thus the user must replace this vector by the correct vector for his application. 13.4.3 DataFlash Boot Sequence The DataFlash boot program performs device initialization followed by the download procedure. The DataFlash boot program supports all Atmel DataFlash devices. parameters to include in the ARM vector 6 for all devices. Table 13-5. Device ...
Page 86
The DataFlash has a Status Register that determines all the parameters required to access the device. The DataFlash boot is configured to be compatible with the future design of the DataFlash. Figure 13-7. Serial DataFlash Download 6221I–ATARM–17-Jul-09 Start Send status ...
Page 87
NAND Flash Boot The NAND Flash Boot program searches for a valid application in the NAND Flash memory. The NAND Flash Boot program searches for a valid application in the NAND Flash memory valid application is found, ...
Page 88
Figure 13-8. AutoBaudrate Flow Diagram – Once the communication interface is identified, the application runs in an infinite Table 13-7. Command 6221I–ATARM–17-Jul-09 Device Setup Character '0x80' received ? ...
Page 89
Mode commands: – Normal mode configures SAM-BA Monitor to send / receive data in binary format, – Terminal mode configures SAM-BA Monitor to send / receive data in ascii format. • Write commands: Write a byte (O), a halfword ...
Page 90
... On Windows systems, the INF files contain the correspondence between vendor ID and product ID. Atmel provides an INF example to see the device as a new serial port and also provides another custom driver used by the SAM-BA application: atm6124.sys. Refer to the document “USB Basic Application” ...
Page 91
Enumeration Process The USB protocol is a master/slave protocol. This is the host that starts the enumeration send- ing requests to the device through the control endpoint. The device handles standard requests as defined in the USB Specification. Table ...
Page 92
The DataFlash and NAND Flash downloaded code size must be inferior to 4096 bytes. • The code is always downloaded from the device address 0x0000_0000 to the address 0x0000_0000 of the internal SRAM (after remap). • The downloaded code ...
Page 93
Real-time Timer (RTT) 14.1 Description The Real-time Timer is built around a 32-bit counter and used to count elapsed seconds. It gen- erates a periodic interrupt and/or triggers an alarm on a programmed value. 14.2 Embedded Characteristics – Real-time ...
Page 94
The Real-time Timer can also be used as a free-running timer with a lower time-base. The best accuracy is achieved by writing RTPRES to 3. Programming RTPRES possible, but may result in losing status events ...
Page 95
Figure 14-2. RTT Counting MCK RTPRES - 1 Prescaler 0 RTT RTTINC (RTT_SR) ALMS (RTT_SR) APB Interface 6221I–ATARM–17-Jul-09 APB cycle ... 0 ALMV-1 ALMV AT91SAM9260 APB cycle ALMV+1 ALMV+2 ALMV+3 read RTT_SR 95 ...
Page 96
Real-time Timer (RTT) User Interface Table 14-1. Register Mapping Offset Register 0x00 Mode Register 0x04 Alarm Register 0x08 Value Register 0x0C Status Register AT91SAM9260 96 Name Access RTT_MR Read-write RTT_AR Read-write RTT_VR Read-only RTT_SR Read-only Reset 0x0000_8000 0xFFFF_FFFF 0x0000_0000 ...
Page 97
Real-time Timer Mode Register Register Name: RTT_MR Access Type: Read/Write 31 30 – – – – • RTPRES: Real-time Timer Prescaler Value Defines the number of SLCK periods required to increment the Real-time ...
Page 98
Real-time Timer Alarm Register Register Name: RTT_AR Access Type: Read/Write • ALMV: Alarm Value Defines the alarm value (ALMV+1) compared with the Real-time Timer. 14.5.3 Real-time Timer Value Register Register Name: ...
Page 99
Real-time Timer Status Register Register Name: RTT_SR Access Type: Read-only 31 30 – – – – – – – – • ALMS: Real-time Alarm Status 0 = The Real-time Alarm has not occurred ...
Page 100
AT91SAM9260 100 6221I–ATARM–17-Jul-09 ...
Page 101
Watchdog Timer (WDT) 15.1 Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period seconds ...
Page 102
Functional Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock supplied with VDDCORE. It restarts with initial values on processor reset. The Watchdog is built around a ...
Page 103
Figure 15-2. Watchdog Behavior FFF Normal behavior WDV Forbidden Window WDD Permitted Window 0 Watchdog Fault AT91SAM9260 103 Watchdog Error WDT_CR = WDRSTT Watchdog Underflow if WDRSTEN WDRSTEN is 0 6221I–ATARM–17-Jul-09 ...
Page 104
Watchdog Timer (WDT) User Interface Table 15-1. Register Mapping Offset Register 0x00 Control Register 0x04 Mode Register 0x08 Status Register AT91SAM9260 104 Name Access WDT_CR Write-only WDT_MR Read-write Once WDT_SR Read-only Reset - 0x3FFF_2FFF 0x0000_0000 6221I–ATARM–17-Jul-09 ...
Page 105
Watchdog Timer Control Register Register Name: WDT_CR Access Type: Write-only – – – – – – • WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the Watchdog. • KEY: Password Should ...
Page 106
Watchdog Timer Mode Register Register Name: WDT_MR Access Type: Read-write Once 31 30 WDIDLEHLT WDDIS WDRPROC WDRSTEN 7 6 • WDV: Watchdog Counter Value Defines the value loaded in the 12-bit Watchdog Counter. • WDFIEN: ...
Page 107
Watchdog Timer Status Register Register Name: WDT_SR Access Type: Read-only 31 30 – – – – – – – – • WDUNF: Watchdog Underflow 0: No Watchdog underflow occurred since the last read ...
Page 108
AT91SAM9260 108 6221I–ATARM–17-Jul-09 ...
Page 109
Periodic Interval Timer (PIT) 16.1 Description The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt designed to offer maximum accuracy and efficient management, even for systems with long response time. 16.2 Embedded Characteristics • Includes ...
Page 110
The first 20-bit CPIV counter increments from programmable overflow value set in the field PIV of the Mode Register (PIT_MR). When the counter CPIV reaches this value, it resets to 0 and increments the Periodic Interval ...
Page 111
Periodic Interval Timer (PIT) User Interface Table 16-1. Register Mapping Offset Register 0x00 Mode Register 0x04 Status Register 0x08 Periodic Interval Value Register 0x0C Periodic Interval Image Register 16.5.1 Periodic Interval Timer Mode Register Register Name: PIT_MR Access Type: ...
Page 112
Periodic Interval Timer Status Register Register Name: PIT_SR Access Type: Read-only 31 30 – – – – – – – – • PITS: Periodic Interval Timer Status 0 = The Periodic Interval timer ...
Page 113
Periodic Interval Timer Image Register Register Name: PIT_PIIR Access Type: Read-only PICNT • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval ...
Page 114
AT91SAM9260 114 ...
Page 115
Shutdown Controller (SHDWC) 17.1 Description The Shutdown Controller controls the power supplies VDDIO and VDDCORE and the wake-up detection on debounced input lines. 17.2 Embedded Characteristics • Shutdown and Wake-up logic – Software programmable assertion of the SHDN pin ...
Page 116
AT91SAM9260 116 6221I–ATARM–17-Jul-09 ...
Page 117
Functional Description The Shutdown Controller manages the main power supply so supplied with VDDBU and manages wake-up input pins and one output pin, SHDN. A typical application connects the pin viding the main power supplies ...
Page 118
Shutdown Controller (SHDWC) User Interface Table 17-2. Register Mapping Offset Register 0x00 Shutdown Control Register 0x04 Shutdown Mode Register 0x08 Shutdown Status Register AT91SAM9260 118 Name Access SHDW_CR Write-only SHDW_MR Read-write SHDW_SR Read-only Reset - 0x0000_0303 0x0000_0000 6221I–ATARM–17-Jul-09 ...
Page 119
Shutdown Control Register Register Name: SHDW_CR Access Type: Write-only – – – – – – • SHDW: Shutdown Command effect KEY is correct, asserts the ...
Page 120
Shutdown Mode Register Register Name: SHDW_MR Access Type: Read/Write 31 30 – – – – CPTWK1 7 6 CPTWK0 • WKMODE0: Wake-up Mode 0 WKMODE[1:0] Wake-up Input Transition Selection 0 0 None. No detection is ...
Page 121
Shutdown Status Register Register Name: SHDW_SR Access Type: Read-only 31 30 – – – – – – – – • WAKEUP0: Wake-up 0 Status wake-up event occurred on the corresponding ...
Page 122
AT91SAM9260 122 6221I–ATARM–17-Jul-09 ...
Page 123
AT91SAM9260 Bus Matrix 18.1 Description The Bus Matrix implements a multi-layer AHB based on the AHB-Lite protocol that enables par- allel access paths between multiple AHB masters and slaves in a system, thus increasing the overall bandwidth. The Bus ...
Page 124
Table 18-1. Master 3 Master 4 Master 5 18.2.2 Matrix Slaves Each Slave has its own arbiter, thus allowing a different arbitration per Slave to be programmed. Table 18-2. Slave 0 Slave 1 Slave 2 Slave 3 Slave 4 18.2.3 ...
Page 125
Special Bus Granting Techniques The Bus Matrix provides some speculative bus granting techniques in order to anticipate access requests from some masters. This mechanism reduces latency at first accesses of a burst or sin- gle transfer. The bus granting ...
Page 126
Arbitration Rules Each arbiter has the ability to arbitrate between two or more different master’s requests. In order to avoid burst breaking and also to provide the maximum throughput for slave interfaces, arbitra- tion may only take place during ...
Page 127
Round-Robin arbitration with fixed default master 18.5.2.1 Round-Robin Arbitration without Default Master This is the main algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to dispatch requests from different masters to the same slave in a ...
Page 128
Bus Matrix User Interface Table 18-4. Register Mapping Offset Register 0x0000 Master Configuration Register 0 0x0004 Master Configuration Register 1 0x0008 Master Configuration Register 2 0x000C Master Configuration Register 3 0x0010 Master Configuration Register 4 0x0014 Master Configuration Register ...
Page 129
Bus Matrix Master Configuration Registers Register Name: MATRIX_MCFG0...MATRIX_MCFG5 Access Type: Read-write 31 30 – – – – – – – – • ULBT: Undefined Length Burst Type 0: Infinite Length Burst No predicted ...
Page 130
Bus Matrix Slave Configuration Registers Register Name: MATRIX_SCFG0...MATRIX_SCFG4 Access Type: Read-write 31 30 – – – – – • SLOT_CYCLE: Maximum Number of Allowed Cycles for a Burst When the SLOT_CYCLE limit is ...
Page 131
Bus Matrix Priority Registers For Slaves Register Name: MATRIX_PRAS0...MATRIX_PRAS4 Access Type: Read-write 31 30 – – – – – – – – • MxPR: Master x Priority Fixed priority of Master x for ...
Page 132
Bus Matrix Master Remap Control Register Register Name: MATRIX_MRCR Access Type: Read-write Reset: 0x0000_0000 31 30 – – – – – – – – • RCBx: Remap Command Bit for AHB Master x ...
Page 133
Chip Configuration User Interface Table 18-5. Chip Configuration User Interface Offset Register 0x0110 - 0x0118 Reserved 0x011C EBI Chip Select Assignment Register 0x0130 - 0x01FC Reserved 6221I–ATARM–17-Jul-09 AT91SAM9260 Name Access – – EBI_CSA Read-write – – Reset Value – ...
Page 134
EBI Chip Select Assignment Register Register Name: EBI_CSA Access Type: Read-write Reset: 0x0001_0000 31 30 – – – – – – – – EBI_CS5A • EBI_CS1A: EBI Chip Select 1 Assignment 0 = ...
Page 135
AT91SAM9260 External Bus Interface 19.1 Description The External Bus Interface (EBI) is designed to ensure the successful data transfer between several external devices and the embedded Memory Controller of an ARM-based device. The Static Memory, SDRAM and ECC Controllers ...
Page 136
Block Diagram 19.2.1 External Bus Interface Figure 19-1 Figure 19-1. Organization of the External Bus Interface Bus Matrix AHB Address Decoders AT91SAM9260 136 shows the organization of the External Bus Interface. External Bus Interface SDRAM Controller MUX Static Logic ...
Page 137
I/O Lines Description Table 19-1. EBI I/O Lines Description Name Function EBI_D0 - EBI_D31 Data Bus EBI_A0 - EBI_A25 Address Bus EBI_NWAIT External Wait Signal EBI_NCS0 - EBI_NCS7 Chip Select Lines EBI_NWR0 - EBI_NWR3 Write Signals EBI_NRD Read Signal ...
Page 138
The connection of some signals through the MUX logic is not direct and depends on the Memory Controller in use at the moment. Table 19-2 on page 138 EBI pins. Table 19-2. AT91SAM9260 138 details the connections between the two ...
Page 139
Application Example 19.4.1 Hardware Interface Table 19-3 on page 139 external devices for each Memory Controller. Table 19-3. EBI Pins and External Static Devices Connections 8-bit Static Signals: Device EBI_ Controller ...
Page 140
Table 19-4. EBI Pins and External Device Connections Signals: EBI_ Controller D15 D16 - D31 A0/NBS0 A1/NWR2/NBS2 A2 - A10 A11 SDA10 A12 A13 - A14 A15 A16/BA0 A17/BA1 A18 - A20 A21/NANDALE A22/NANDCLE A23 ...
Page 141
Table 19-4. EBI Pins and External Device Connections (Continued) Signals: EBI_ Controller CFCE2 SDCK SDCKE RAS CAS SDWE NWAIT (2) Pxx (2) Pxx (2) Pxx Notes: 1. Not directly connected to the CompactFlash slot. Permits the control of the bidirectional ...
Page 142
Connection Examples Figure 19-2 Figure 19-2. EBI Connections to Memory Devices EBI D0-D31 RAS CAS SDCK SDCKE SDWE A0/NBS0 NWR1/NBS1 A1/NWR2/NBS2 NWR3/NBS3 NRD/NOE NWR0/NWE SDA10 A2-A15 A16/BA0 A17/BA1 A18-A25 NCS0 NCS1/SDCS NCS2 NCS3 NCS4 NCS5 19.5 Product Dependencies 19.5.1 ...
Page 143
ECC Controller (ECC) • a chip select assignment feature that assigns an AHB address space to the external devices • a multiplex controller circuit that shares the pins between the different Memory Controllers • programmable CompactFlash support logic ...
Page 144
I/O Mode, Common Memory Mode, Attribute Memory Mode and True IDE Mode Within the NCS4 and/or NCS5 address space, the current transfer address is used to distinguish I/O mode, common memory mode, attribute memory mode and True IDE mode. ...
Page 145
The CFCE1 and CFCE2 waveforms are identical to the corresponding NCSx waveform. For details on these waveforms and timings, refer to the Static Memory Controller section. Table 19-6. CFCE1 and CFCE2 Truth Table Mode CFCE2 Attribute Memory NBS1 NBS1 Common ...
Page 146
Figure 19-4. CompactFlash Read/Write Control Signals External Bus Interface SMC NWR0_NWE Table 19-7. CompactFlash Mode Selection Mode Base Address CFOE Attribute Memory Common Memory I/O Mode True IDE Mode 19.6.6.4 Multiplexing of CompactFlash Signals on EBI Pins Table 19-8 on ...
Page 147
Table 19-9. Shared CompactFlash Interface Multiplexing Pins NRD/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW A25/CFRNW 19.6.6.5 Application Example Figure 19-5 on page 148 CFRNW signals are not directly connected to the CompactFlash slot 0, but do control the direc- tion and the output ...
Page 148
Figure 19-5. CompactFlash Application Example EBI D[15:0] A25/CFRNW NCS4/CFCS0 CD (PIO) A[10:0] A22/REG NOE/CFOE NWE/CFWE NWR1/CFIOR NWR3/CFIOW CFCE1 CFCE2 NWAIT 19.6.7 NAND Flash Support The External Bus Interface integrates circuitry that interfaces to NAND Flash devices. 19.6.7.1 External Bus Interface ...
Page 149
Figure 19-6. NAND Flash Signal Multiplexing on EBI Pins SMC NWR0_NWE 19.6.7.2 NAND Flash Signals The address latch enable and command latch enable signals on the NAND Flash device are driven by address bits A22 and A21 of the EBI ...
Page 150
Note: 19.7 Implementation Examples The following hardware configurations are given for illustration only. The user should refer to the memory manufacturer web site to check current device availability. AT91SAM9260 150 The External Bus Interface is also able to support 16-bit ...
Page 151
SDRAM 19.7.1.1 Hardware Configuration D[0..15] A[0..14] (Not used A12) 19.7.1.2 Software Configuration The following configuration has to be performed: • Assign the EBI CS1 to the SDRAM controller by setting the bit EBI_CS1A in the EBI Chip Select ...
Page 152
SDRAM 19.7.2.1 Hardware Configuration D[0..31] A[0..14] (Not used A12 A10 A11 SDA10 SDA10 A13 BA0 BA0 BA1 BA1 A14 SDCKE SDCKE SDCK SDCK 1%6 A0 1%6 CFIOR_NBS1_NWR1 CAS CAS RAS ...
Page 153
NAND Flash 19.7.3.1 Hardware Configuration D[0..7] CLE ALE NANDOE NANDWE (ANY PIO) (ANY PIO) 19.7.3.2 Software Configuration The following configuration has to be performed: • Assign the EBI CS3 to the NAND Flash by setting the bit EBI_CS3A ...
Page 154
NAND Flash 19.7.4.1 Hardware Configuration D[0..15] CLE ALE NANDOE NANDWE (ANY PIO) (ANY PIO) 19.7.4.2 Software Configuration The software configuration is the same as for an 8-bit NAND Flash except the data bus width programmed in the mode ...
Page 155
NOR Flash on NCS0 19.7.5.1 Hardware Configuration D[0..15] A[1..22] NRST NWE NCS0 NRD 19.7.5.2 Software Configuration The default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled by Chip Select, allows boot on 16-bit ...
Page 156
Compact Flash 19.7.6.1 Hardware Configuration D[0..15] D15 D14 D13 D12 D11 D10 A25/CFRNW 4 CFCSx (CFCS0 or CFCS1) 5 (ANY PIO) &$5' '(7(&7 A[0..10] A10 ...
Page 157
Software Configuration The following configuration has to be performed: • Assign the EBI CS4 and/or EBI_CS5 to the CompactFlash Slot 0 or/and Slot 1 by setting the bit EBI_CS4A or/and EBI_CS5A in the EBI Chip Select Assignment Register located ...
Page 158
Compact Flash True IDE 19.7.7.1 Hardware Configuration D[0..15] D15 D14 D13 D12 D11 D10 A25/CFRNW 4 CFCSx (CFCS0 or CFCS1) 5 (ANY PIO) &$5' '(7(&7 A[0..10] A10 A9 A8 ...
Page 159
Software Configuration The following configuration has to be performed: • Assign the EBI CS4 and/or EBI_CS5 to the CompactFlash Slot 0 or/and Slot 1 by setting the bit EBI_CS4A or/and EBI_CS5A in the EBI Chip Select Assignment Register located ...
Page 160
AT91SAM9260 160 6221I–ATARM–17-Jul-09 ...
Page 161
Static Memory Controller (SMC) 20.1 Description The Static Memory Controller (SMC) generates the signals that control the access to the exter- nal memory devices or peripheral devices. It has 8 Chip Selects and a 26-bit address bus. The 32-bit ...
Page 162
Application Example 20.4.1 Hardware Interface Figure 20-1. SMC Connections to Static Memory Devices D0-D31 A0/NBS0 NWR0/NWE NWR1/NBS1 A1/NWR2/NBS2 NWR3/NBS3 NCS0 NCS1 NCS2 NCS3 NCS4 NCS5 NCS6 NCS7 A2 - A25 Static Memory Controller 20.5 Product Dependencies 20.5.1 I/O Lines ...
Page 163
External Memory Mapping The SMC provides address lines, A[25:0]. This allows each chip select line to address Mbytes of memory. If the physical memory device connected on one chip select is smaller than ...
Page 164
Figure 20-3. Memory Connection for an 8-bit Data Bus Figure 20-4. Memory Connection for a 16-bit Data Bus Figure 20-5. Memory Connection for a 32-bit Data Bus SMC AT91SAM9260 164 D[7:0] A[18:2] A0 SMC A1 NWE NRD NCS[2] D[15:0] A[19:2] ...
Page 165
Byte Write Access Byte write access supports one byte write signal per byte of the data bus and a single read signal. Note that the SMC does not allow boot in Byte Write Access mode. • For 16-bit devices: ...
Page 166
Figure 20-6. Connection 8-bit Devices on a 16-bit Bus: Byte Write Option 20.7.2.3 Signal Multiplexing Depending on the BAT, only the write signals or the byte select signals are used. To save IOs at the external bus ...
Page 167
Figure 20-7. Connection of 2x16-bit Data Bus on a 32-bit Data Bus (Byte Select Option) SMC Table 20-3. SMC Multiplexed Signal Translation Signal Name Device Type 1x32-bit Byte Access Type (BAT) Byte Select NBS0_A0 NBS0 NWE_NWR0 NWE NBS1_NWR1 NBS1 NBS2_NWR2_A1 ...
Page 168
Read Waveforms The read cycle is shown on The read cycle starts with the address setting on the memory address bus, i.e.: {A[25:2], A1, A0} for 8-bit devices {A[25:2], A1} for 16-bit devices A[25:2] for 32-bit devices. Figure 20-8. ...
Page 169
NCS Waveform Similarly, the NCS signal can be divided into a setup time, pulse length and hold time: 1. NCS_RD_SETUP: the NCS setup time is defined as the setup time of address before the NCS falling edge. 2. NCS_RD_PULSE: ...
Page 170
Figure 20-9. No Setup, No Hold On NRD and NCS Read Signals MCK A[25:2] NBS0,NBS1, NBS2,NBS3, A0, A1 NRD NCS D[31:0] 20.8.1.5 Null Pulse Programming null pulse is not permitted. Pulse must be at least set null ...
Page 171
Figure 20-10. READ_MODE = 1: Data is sampled by SMC before the rising edge of NRD MCK A[25:2] NBS0,NBS1, NBS2,NBS3, A0, A1 NRD NCS D[31:0] 20.8.2.2 Read is Controlled by NCS (READ_MODE = 0) Figure 20-11 the falling edge of ...
Page 172
Write Waveforms The write protocol is similar to the read protocol depicted in starts with the address setting on the memory address bus. 20.8.3.1 NWE Waveforms The NWE signal is characterized by a setup timing, a pulse ...
Page 173
Write Cycle The write_cycle time is defined as the total duration of the write cycle, that is, from the time where address is set on the address bus to the point where address may change. The total write cycle ...
Page 174
Write Mode The WRITE_MODE parameter in the SMC_MODE register of the corresponding chip select indi- cates which signal controls the write operation. 20.8.4.1 Write is Controlled by NWE (WRITE_MODE = 1): Figure 20-14 put on the bus during the ...
Page 175
Figure 20-15. WRITE_MODE = 0. The write operation is controlled by NCS MCK [25:2] A NBS0, NBS1, NBS2, NBS3, A0, A1 NWE, NWR0, NWR1, NWR2, NWR3 NCS D[31:0] 20.8.5 Coding Timing Parameters All timing parameters are defined for one chip ...
Page 176
Reset Values of Timing Parameters Table 20-5 Table 20-5. Register SMC_SETUP SMC_PULSE SMC_CYCLE WRITE_MODE READ_MODE 20.8.7 Usage Restriction The SMC does not check the validity of the user-programmed parameters. If the sum of SETUP and PULSE parameters is larger ...
Page 177
Figure 20-16. Chip Select Wait State between a Read Access on NCS0 and a Write Access on NCS2 MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NRD NWE NCS0 NCS2 D[31:0] 20.9.2 Early Read Wait State In some cases, the SMC ...
Page 178
Figure 20-17. Early Read Wait State: Write with No Hold Followed by Read with No Setup MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 NWE NRD D[31:0] Figure 20-18. Early Read Wait State: NCS Controlled Write with No Hold Followed ...
Page 179
Figure 20-19. Early Read Wait State: NWE-controlled Write with No Hold Followed by a Read with one Set-up Cycle A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 internal write controlling signal external write controlling signal (NWE) D[31:0] 20.9.3 Reload User Configuration ...
Page 180
Read to Write Wait State Due to an internal mechanism, a wait cycle is always inserted between consecutive read and write SMC accesses. This wait cycle is referred read to write wait state in this document. ...
Page 181
Data Float Wait States Some memory devices are slow to release the external bus. For such devices necessary to add wait states (data float wait states) after a read access: • before starting a read access to ...
Page 182
Figure 20-20. TDF Period in NRD Controlled Read Access (TDF = 2) MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 NRD NCS D[31:0] Figure 20-21. TDF Period in NCS Controlled Read Operation (TDF = 3) MCK A[25:2] NBS0, NBS1, NBS2, ...
Page 183
TDF Optimization Enabled (TDF_MODE = 1) When the TDF_MODE of the SMC_MODE register is set to 1 (TDF optimization is enabled), the SMC takes advantage of the setup period of the next access to optimize the number of wait ...
Page 184
Figure 20-23. TDF Optimization Disabled (TDF Mode = 0). TDF wait states between 2 read accesses on different chip selects MCK 25:2] A[ NBS0, NBS1, NBS2, NBS3, A0, A1 read1 controlling signal (NRD) read2 controlling signal (NRD) D[31:0] read1 cycle ...
Page 185
Figure 20-25. TDF Mode = 0: TDF wait states between read and write accesses on the same chip select MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 read1 controlling signal (NRD) write2 controlling signal (NWE) D[31:0] TDF_CYCLES = 5 20.11 ...
Page 186
Frozen Mode When the external device asserts the NWAIT signal (active low), and after internal synchroniza- tion of this signal, the SMC state is frozen, i.e., SMC internal counters are frozen, and all control signals remain unchanged. When the ...
Page 187
Figure 20-27. Read Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10) MCK [25:2] A NBS0, NBS1, NBS2, NBS3, A0,A1 4 NCS 1 NRD NWAIT internally synchronized NWAIT signal 6221I–ATARM–17-Jul-09 FROZEN STATE ...
Page 188
Ready Mode In Ready mode (EXNW_MODE = 11), the SMC behaves differently. Normally, the SMC begins the access by down counting the setup and pulse counters of the read/write controlling signal. In the last cycle of the pulse phase, ...
Page 189
Figure 20-29. NWAIT Assertion in Read Access: Ready Mode (EXNW_MODE = 11) MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 6 NCS NRD NWAIT internally synchronized NWAIT signal 6221I–ATARM–17-Jul- Read cycle EXNW_MODE = ...
Page 190
NWAIT Latency and Read/write Timings There may be a latency between the assertion of the read/write controlling signal and the asser- tion of the NWAIT signal by the device. The programmed pulse length of the read/write controlling signal must ...
Page 191
Slow Clock Mode The SMC is able to automatically apply a set of “slow clock mode” read/write waveforms when an internal signal driven by the Power Management Controller is asserted because MCK has been turned to a very slow ...
Page 192
Switching from (to) Slow Clock Mode to (from) Normal Mode When switching from slow clock mode to the normal mode, the current slow clock mode transfer is completed at high clock rate, with the set of slow clock mode ...
Page 193
Figure 20-33. Recommended Procedure to Switch from Slow Clock Mode to Normal Mode or from Normal Mode to Slow Clock Mode Slow Clock Mode internal signal from PMC MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NWE 1 NCS SLOW CLOCK ...
Page 194
Asynchronous Page Mode The SMC supports asynchronous burst reads in page mode, providing that the page mode is enabled in the SMC_MODE register (PMEN field). The page size must be configured in the SMC_MODE register (PS field ...
Page 195
NCS_RD_PULSE field of the SMC_PULSE register. The pulse length of subsequent accesses within the page are defined using the NRD_PULSE parameter. In page mode, the programming of the read timings is described in Table 20-8. Parameter READ_MODE NCS_RD_SETUP NCS_RD_PULSE NRD_SETUP ...
Page 196
Figure 20-35. Access to Non-sequential Data within the Same Page MCK A[25:3] A[2], A1, A0 NRD NCS D[7:0] 6221I–ATARM–17-Jul-09 Page address A1 D1 NRD_PULSE NCS_RD_PULSE AT91SAM9260 NRD_PULSE 196 ...
Page 197
Static Memory Controller (SMC) User Interface The SMC is programmed using the registers listed in gram the parameters of the external device connected on it bytes (0x10) are required per chip select. The user must complete writing ...
Page 198
SMC Setup Register Register Name: SMC_SETUP[0..7] Access Type: Read-write 31 30 – – – – – – – – • NWE_SETUP: NWE Setup Length The NWE signal setup length is defined as: NWE ...
Page 199
SMC Pulse Register Register Name: SMC_PULSE[0..7] Access Type: Read-write 31 30 – – – – • NWE_PULSE: NWE Pulse Length The NWE signal pulse length is defined as: NWE pulse length = (256* ...
Page 200
SMC Cycle Register Register Name: SMC_CYCLE[0..7] Access Type: Read-write 31 30 – – – – • NWE_CYCLE: Total Write Cycle Length The total write cycle length is the total duration in clock cycles ...