DSPIC30F6012-20E/PF Microchip Technology, DSPIC30F6012-20E/PF Datasheet - Page 9

• Manufacturer Part Number: DSPIC30F6012-20E/PF
• Description: IC DSPIC MCU/DSP 144K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6012-20E/PF

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 144KB (48K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: XLT64PT4 - SOCKET TRAN ICE 64MQFP/TQFPAC164313 - MODULE SKT FOR PM3 64PFAC30F002 - MODULE SOCKET DSPIC30F 64TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DSPIC30F601220EPF

8. Module: Data Memory
EXAMPLE 6:
EXAMPLE 7:
© 2010 Microchip Technology Inc.
:Unexpected Results!
:Correct Results!
When an instruction that writes to a location in the
address range of Y data memory (addresses
between 0x1800 and 0x27FF) is immediately
followed by a MAC-type DSP instruction that reads
a location also resident in Y data memory, the two
operations will not be executed as specified. This
is demonstrated in Example 6.
Work arounds
Work around 1:
Insert a NOP between the two instructions as
shown in Example 7.
Work around 2:
If work around #1 is not feasible due to application
real-time
precautions to ensure that a write operation
performed on a location in Y data memory is not
immediately
instruction that performs a read operation of a
location in Y data memory.
Affected Silicon Revisions
MOV
MOV
MOV
MAC
MOV
MOV
MOV
NOP
MAC
A3
X
B1
X
#0x190A, W0
#0x19B0, W10
W2, [W0++]
W4*W5, A, [W10]+=2, W5 ;Perform
#0x190A, W0
#0x19B0, W10
W2, [W0++]
W4*W5, A, [W10]+=2, W5 ;Perform
constraints,
B2
followed
X
INCORRECT RESULTS
CORRECT RESULTS
by
the
;Load address > =
;0x1800 into W0
;Load address >=
;0x1800 into W10
;Perform indirect
;write via W0 to
;address >= 0x1800
;read operation
;using Y-AGU
;Load address > =
;0x1800 into W0
;Load address >=
;0x1800 into W10
;Perform indirect
;write via W0 to
;address >= 0x1800
;No operation
;read operation
;using Y-AGU
a
user
DSP
may
MAC-type
take
dsPIC30F6011/6012/6013/6014
9. Module: Interrupt Controller
EXAMPLE 8:
.global
__MathError:
Catastrophic accumulator overflow traps are
enabled as follows:
A carry generated out of bit 39 in the accumulator
causes a catastrophic overflow of the accumulator
since the sign bit has been destroyed. If a math
error trap handler has been defined, the processor
will vector to the math error trap handler upon a
catastrophic overflow.
If the respective Accumulator Overflow status bit,
OA or OB (SR<15/14>), is not cleared within the
trap handler routine prior to exiting the trap handler
routine, the processor will immediately re-enter the
trap handler routine.
Work around
If a math error trap occurs due to a catastrophic
accumulator overflow, the overflow status flags,
OA and/or OB (SR<15:14>), should be cleared
within the trap handler routine. Subsequently, the
MATHERR (INTCON1<4>) flag bit should be
cleared within the trap handler prior to executing
the RETFIE instruction.
Since the OA and OB bits are read-only bits, it will be
necessary to execute a dummy accumulator-based
instruction within the trap service routine in order to
clear these status bits, and eventually clear the
MATHERR trap flag. This is shown in Example 8.
Affected Silicon Revisions
A3
- COVTE (INTCON1<8>) = 1
- SATA/SATB (CORCON <7:6>) = 0
X
B1
X
__MathError
B2
BTSC
CLR
BTSC
CLR
BCLR
RETFIE
X
USING DUMMY DSP
INSTRUCTION
SR, #OA
A
SR, #OB
B
INTCON1, #MATHERR
DS80456D-page 9