AT32UC3A1256-AUT Atmel, AT32UC3A1256-AUT Datasheet - Page 524
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AT32UC3A1256-AUT
Manufacturer Part Number
AT32UC3A1256-AUT
Description
IC MCU AVR32 256KB FLASH 100TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A1256-AUT
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Package
100TQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
66 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
69
Interface Type
Ethernet/I2S/JTAG/SPI/TWI/USART
Number Of Timers
3
Controller Family/series
AT32UC3A
No. Of I/o's
69
Ram Memory Size
64KB
Cpu Speed
66MHz
No. Of Timers
1
Rohs Compliant
Yes
Processor Series
AT32UC3x
Core
AVR32
Data Ram Size
64 KB
Maximum Clock Frequency
66 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105
Minimum Operating Temperature
- 40 C
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFPATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Figure 30-24. Pipe Activation Algorithm
30.7.3.7
30.7.3.8
32058J–AVR32–04/11
Address Setup
Remote Wake-Up
As long as the pipe is not correctly configured (CFGOK = 0), the controller can not send packets
to the device through this pipe.
The CFGOK bit is set by hardware only if the configured size and number of banks are correct
compared to their maximal allowed values for the pipe (see
maximal FIFO size (i.e. the DPRAM size).
See
Once the pipe is correctly configured (CFGOK = 1), only the PTOKEN and INTFRQ bit-fields can
be modified by software. INTFRQ is meaningless for non-interrupt pipes.
When starting an enumeration, the firmware gets the device descriptor by sending a
GET_DESCRIPTOR USB request. This descriptor contains the maximal packet size of the
device default control endpoint (bMaxPacketSize0) and the firmware re-configures the size of
the default control pipe with this size parameter.
Once the device has answered the first host requests with the default device address 0, the host
assigns a new address to the device. The host controller has to send a USB reset to the device
and to send a SET_ADDRESS(addr) SETUP request with the new address to be used by the
device. Once this SETUP transaction is over, the firmware writes the new address into the
HADDR bit-field. All following requests, on all pipes, will be performed using this new address.
When the host controller sends a USB reset, the HADDR bit-field is reset by hardware and the
following host requests will be performed using the default device address 0.
The controller host mode enters the Suspend state when the SOFE bit is cleared. No more
“Start of Frame” is sent on the USB bus and the USB device enters the Suspend state 3 ms
later.
The device awakes the host by sending an Upstream Resume (Remote Wake-Up feature).
When the host controller detects a non-idle state on the USB bus, it raises the Host Wake-Up
Section 30.7.1.6 on page 506
Pipe Activated
Yes
CFGOK ==
PENX = 1
Activation
UPCFGX
PEPNUM
PTOKEN
INTFRQ
PTYPE
ALLOC
PSIZE
Pipe
PBK
1?
No
ERROR
for more details about DPRAM management.
Enable the pipe.
Configure the pipe:
Allocate the configured DPRAM
banks.
Test if the pipe configuration is
correct.
- interrupt request frequency;
- endpoint number;
- type;
- token;
- size;
- number of banks.
Table 30-1 on page
AT32UC3A
497) and to the
524
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