AT32UC3A1256-AUT Atmel, AT32UC3A1256-AUT Datasheet - Page 272
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AT32UC3A1256-AUT
Manufacturer Part Number
AT32UC3A1256-AUT
Description
IC MCU AVR32 256KB FLASH 100TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A1256-AUT
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Package
100TQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
66 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
69
Interface Type
Ethernet/I2S/JTAG/SPI/TWI/USART
Number Of Timers
3
Controller Family/series
AT32UC3A
No. Of I/o's
69
Ram Memory Size
64KB
Cpu Speed
66MHz
No. Of Timers
1
Rohs Compliant
Yes
Processor Series
AT32UC3x
Core
AVR32
Data Ram Size
64 KB
Maximum Clock Frequency
66 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105
Minimum Operating Temperature
- 40 C
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFPATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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25.7.8
25.7.9
32058J-AVR32-04/11
Loop Mode
Interrupt
Figure 25-14. Transmit Frame Format in Continuous Mode
Note:
Figure 25-15. Receive Frame Format in Continuous Mode
Note:
The receiver can be programmed to receive transmissions from the transmitter. This is done by
setting the Loop Mode (LOOP) bit in RFMR. In this case, RX_DATA is connected to TX_DATA,
RX_FRAME_SYNC is connected to TX_FRAME_SYNC and RX_CLOCK is connected to
TX_CLOCK.
Most bits in SR have a corresponding bit in interrupt management registers.
The SSC can be programmed to generate an interrupt when it detects an event. The interrupt is
controlled by writing IER (Interrupt Enable Register) and IDR (Interrupt Disable Register) These
registers enable and disable, respectively, the corresponding interrupt by setting and clearing
the corresponding bit in IMR (Interrupt Mask Register), which controls the generation of inter-
rupts by asserting the SSC interrupt line connected to the interrupt controller.
1. STTDLY is set to 0. In this example, THR is loaded twice. FSDEN value has no effect on the
1. STTDLY is set to 0.
transmission. SyncData cannot be output in continuous mode.
TX_DATA
Start: 1. TXEMPTY set to 1
RX_DATA
2. Write into the THR
Start
From THR
DATLEN
Start = Enable Receiver
Data
DATLEN
To RHR
Data
From THR
DATLEN
Data
DATLEN
To RHR
Data
Default
AT32UC3A
272
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