DSPIC30F6010A-30I/PT Microchip Technology, DSPIC30F6010A-30I/PT Datasheet - Page 9
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DSPIC30F6010A-30I/PT
Manufacturer Part Number
DSPIC30F6010A-30I/PT
Description
IC DSPIC MCU/DSP 144K 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F6011A-30IPT.pdf
(6 pages)
2.DSPIC30F6015-30IPT.pdf
(232 pages)
3.DSPIC30F6015-30IPT.pdf
(14 pages)
4.DSPIC30F6015-30IPT.pdf
(12 pages)
5.DSPIC30F6015-30IPT.pdf
(18 pages)
6.DSPIC30F6010A-30IPF.pdf
(22 pages)
7.DSPIC33FJ128MC506-IPT.pdf
(24 pages)
Specifications of DSPIC30F6010A-30I/PT
Program Memory Type
FLASH
Program Memory Size
144KB (48K x 24)
Package / Case
80-TFQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
68
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC30F
Core
dsPIC
Maximum Clock Frequency
30 MHz
Number Of Programmable I/os
68
Data Ram Size
8 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, ICE4000, DM240002, DM300020, DM330011, DM300019
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM300019 - BOARD DEMO DSPICDEM 80L STARTERXLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC30F007 - MODULE SKT FOR DSPIC30F 80TQFPDM300020 - BOARD DEV DSPICDEM MC1 MOTORCTRLDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
DSPIC30F6010A30IP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F6010A-30I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
DSPIC30F6010A-30I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
14. Module: I
15. Module: I
16. Module: I
© 2008 Microchip Technology Inc.
If there are two I
them is acting as the Master receiver and the other
as the Slave transmitter. If both devices are config-
ured for 10-bit addressing mode, and have the
same value in the A10 and A9 bits of their
addresses, then when the Slave select address is
sent from the Master, both the Master and Slave
acknowledge it. When the Master sends out the
read operation, both the Master and the Slave
enter into Read mode and both of them transmit
the data. The resultant data will be the ANDing of
the two transmissions.
Work around
In all I
A10 and A9 should be different.
In 10-bit Addressing mode, some address
matches don't set the RBF flag or load the receive
register I2CxRCV, if the lower address byte
matches the reserved addresses. In particular,
these include all addresses with the form
XX0000XXXX
following exceptions:
• 001111000X
• 011111001X
• 101111010X
• 111111011X
Work around
Ensure that the lower address byte in 10-bit
Addressing mode does not match any 7-bit
reserved addresses.
When the I
slave with and address of 0x102, the I2CxRCV
register content for the lower address byte is 0x01
rather
acknowledges both address bytes.
Work around
None.
2
C devices, the addresses as well as bits
than
2
2
2
2
C
C
C
C module is configured as a 10-bit
0x02;
and
2
C devices on the bus, one of
XX1111XXXX,
however,
the
with
module
the
dsPIC30F6010A/6015
17. Module: I
Note:
When the I
I2CEN bit in the I2CCON register, the dsPIC DSC
device generates a glitch on the SDA and SCL
pins. This glitch falsely indicates “Communication
Start” to all devices on the I
a bus collision in a multi-master configuration.
Additionally, when the I2CEN bit is set, the S and
P bits of the I
‘0’, respectively, which indicate a “Communication
Start” condition.
Work arounds
To avoid this issue, either of the following two work
arounds can be implemented, depending on the
application requirements.
Work around 1:
In a single-master environment, add a delay
between enabling the I
transmission. The delay should be equal to or
greater than the time it takes to transmit two data
bits.
In the multi-master configuration, in addition to the
delay, all other I
nized and wait for the I
before initiating any kind of communication.
Work around 2:
In dsPIC DSC devices in which the I
multiplexed
precedence in the use of the pin, it is possible to
avoid this glitch by enabling the higher priority
module before enabling the I
Use the following procedure to implement this
work around:
1. Enable the higher priority peripheral module
2. Set up and enable the I
3. Disable the higher priority peripheral module
that is multiplexed on the same pins as the I
module.
that was enabled in step 1.
Work around 2 works only for devices that
share the SDA and SCL pins with another
peripheral that has a higher precedence
over the port latch, such as the UART. The
priority is shown in the pin diagram located
in the data sheet. For example, if the SDA
and SCL pins are shared with the UART
and SPI pins, and the UART has higher
precedence on the port latch pin.
2
2
C
C module is enabled by setting the
2
with
C module are set to values ‘1’ and
2
C masters should be synchro-
other
2
2
C module and the first data
C module to be initialized
2
2
modules
C bus, and can cause
C module.
2
C module.
DS80400A-page 9
2
C module is
that
have
2
C