ATMEGA64L-8AU Atmel, ATMEGA64L-8AU Datasheet - Page 141

• Manufacturer Part Number: ATMEGA64L-8AU
• Description: IC AVR MCU 64K 8MHZ 3V 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64L-8AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Package: 64TQFP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 53
• Interface Type: JTAG/SPI/TWI/USART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 4
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 8 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• Cpu Family: ATmega
• Device Core Size: 8b
• Frequency (max): 8MHz
• Total Internal Ram Size: 4KB
• # I/os (max): 53
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Supply Voltage (max): 5.5/5.8V
• Operating Supply Voltage (min): 2.4/2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: TQFP
• Controller Family/series: AVR MEGA
• No. Of I/o's: 53
• Eeprom Memory Size: 2KB
• Ram Memory Size: 4KB
• Cpu Speed: 8MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFPATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ETIMSK – Extended
Timer/Counter
Interrupt Mask
Register
2490Q–AVR–06/10
(1)
• Bit 2 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Overflow Interrupt is enabled. The corresponding Interrupt Vector
(see “Interrupts” on page 61) is executed when the TOV1 flag, located in TIFR, is set.
Note:
• Bit 7:6 – Reserved Bits
These bits are reserved for future use. For ensuring compatibility with future devices, these bits
must be set to zero when ETIMSK is written.
• Bit 5 – TICIE3: Timer/Counter3, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter3 Input Capture interrupt is enabled. The corresponding Interrupt
Vector (see “Interrupts” on page 61) is executed when the ICF3 flag, located in ETIFR, is set.
• Bit 4 – OCIE3A: Timer/Counter3, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter3 Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 61) is executed when the OCF3A flag, located in
ETIFR, is set.
• Bit 3 – OCIE3B: Timer/Counter3, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter3 Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 61) is executed when the OCF3B flag, located in
ETIFR, is set.
• Bit 2 – TOIE3: Timer/Counter3, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter3 Overflow Interrupt is enabled. The corresponding Interrupt Vector
(see “Interrupts” on page 61) is executed when the TOV3 flag, located in ETIFR, is set.
• Bit 1 – OCIE3C: Timer/Counter3, Output Compare C Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter3 Output Compare C Match interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 61) is executed when the OCF3C flag, located in
ETIFR, is set.
• Bit 0 – OCIE1C: Timer/Counter1, Output Compare C Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare C Match interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 61) is executed when the OCF1C flag, located in
ETIFR, is set.
Bit
(0x7D)
Read/Write
Initial Value
1. This register is not available in ATmega103 compatibility mode.
R
7
–
0
R
6
–
0
TICIE3
R/W
5
0
OCIE3A
R/W
4
0
OCIE3B
R/W
3
0
TOIE3
R/W
2
0
OCIE3C
R/W
1
0
ATmega64(L)
OCIE1C
R/W
0
0
ETIMSK
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