ATMEGA640V-8AU Atmel, ATMEGA640V-8AU Datasheet - Page 109
![IC MCU AVR 64K FLASH 100-TQFP](/photos/6/70/67048/313-100-tqfp_sml.jpg)
ATMEGA640V-8AU
Manufacturer Part Number
ATMEGA640V-8AU
Description
IC MCU AVR 64K FLASH 100-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA640V-8AU
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
86
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Processor Series
ATMEGA64x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
2-Wire, JTAG, SPI
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
86
Number Of Timers
8
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Controller Family/series
AVR MEGA
No. Of I/o's
86
Eeprom Memory Size
4KB
Ram Memory Size
8KB
Cpu Speed
8MHz
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK503 - STARTER KIT AVR EXP MODULE 100P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA640V-8AU
Manufacturer:
PHILIPS
Quantity:
56
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13.3
2549M–AVR–09/10
Moving Interrupts Between Application and Boot Section
When the BOOTRST Fuse is programmed and the Boot section size set to 8 Kbytes, the most
typical and general program setup for the Reset and Interrupt Vector Addresses is:
When the BOOTRST Fuse is programmed, the Boot section size set to 8 Kbytes and the IVSEL
bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general
program setup for the Reset and Interrupt Vector Addresses is:
The MCU Control Register controls the placement of the Interrupt Vector table, see Code Exam-
ple below. For more details, see
Address Labels Code
.org 0x0002
0x00002
0x00004
...
0x00070
;
.org 0x1F000
0x1F000 RESET: ldi
0x1F001
0x1F002
0x1F003
0x1F004
0x1F005
Address
;
.org 0x1F000
0x1F000
0x1F002
0x1F004
...
0x1F070
;
0x1F072
0x1F073
0x1F074
0x1F075
0x1F076
0x1FO77
Labels Code
RESET: ldi
jmp
jmp
...
jmp
out
ldi
out
sei
<instr>
jmp
jmp
jmp
...
jmp
out
ldi
out
sei
<instr>
EXT_INT0
EXT_INT1
...
USART3_TXC
r16,high(RAMEND); Main program start
SPH,r16
r16,low(RAMEND)
SPL,r16
RESET
EXT_INT0
EXT_INT1
...
USART3_TXC
r16,high(RAMEND) ; Main program start
SPH,r16
r16,low(RAMEND)
SPL,r16
xxx
ATmega640/1280/1281/2560/2561
“Reset and Interrupt Handling” on page
xxx
Comments
; IRQ0 Handler
; IRQ1 Handler
;
; USART3 TX Complete Handler
; Set Stack Pointer to top of RAM
; Enable interrupts
Comments
; Reset handler
; IRQ0 Handler
; IRQ1 Handler
;
; USART3 TX Complete Handler
; Set Stack Pointer to top of RAM
; Enable interrupts
18.
109
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