AT32UC3B1256-AUT Atmel, AT32UC3B1256-AUT Datasheet - Page 330
![IC MCU AVR32 256KB FLASH 48-TQFP](/photos/6/82/68248/313-48-vqfp_sml.jpg)
AT32UC3B1256-AUT
Manufacturer Part Number
AT32UC3B1256-AUT
Description
IC MCU AVR32 256KB FLASH 48-TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3B1256-AUT
Core Processor
AVR
Core Size
32-Bit
Speed
60MHz
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
28
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TQFP, 48-VQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire/SPI/USART
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
28
Number Of Timers
3
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1101
Minimum Operating Temperature
- 40 C
On-chip Adc
6-ch x 10-bit
Controller Family/series
AVR UC3
No. Of I/o's
28
Ram Memory Size
32KB
Cpu Speed
60MHz
No. Of Timers
1
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP48 - STK600 SOCKET/ADAPTER 48-TQFPATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3B1256-AUT
Manufacturer:
ATMEL
Quantity:
1 000
- Current page: 330 of 692
- Download datasheet (11Mb)
21.6.8
21.6.8.1
32059K–03/2011
SPI Mode
Modes of Operation
The Serial Peripheral Interface (SPI) Mode is a synchronous serial data link that provides com-
munication with external devices in Master or Slave Mode. It also enables communication
between processors if an external processor is connected to the system.
The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to
other SPIs. During a data transfer, one SPI system acts as the “master” which controls the data
flow, while the other devices act as “slaves'' which have data shifted into and out by the master.
Different CPUs can take turns being masters and one master may simultaneously shift data into
multiple slaves. (Multiple Master Protocol is the opposite of Single Master Protocol, where one
CPU is always the master while all of the others are always slaves.) However, only one slave
may drive its output to write data back to the master at any given time.
A slave device is selected when its NSS signal is asserted by the master. The USART in SPI
Master mode can address only one SPI Slave because it can generate only one NSS signal.
Nevertheless the user can use standard I/O lines to access more than one SPI slave.
The SPI system consists of two data lines and two control lines:
The USART can operate in Master Mode or in Slave Mode.
Operation in SPI Master Mode is programmed by writing at 0xE the MODE field in the Mode
Register. In this case the SPI lines must be connected as described below:
Operation in SPI Slave Mode is programmed by writing at 0xF the MODE field in the Mode Reg-
ister. In this case the SPI lines must be connected as described below:
In order to avoid unpredicted behavior, any change of the SPI Mode must be followed by a soft-
ware reset of the transmitter and of the receiver (except the initial configuration after a hardware
reset).
• Master Out Slave In (MOSI): This data line supplies the output data from the master shifted
• Master In Slave Out (MISO): This data line supplies the output data from a slave to the input
• Serial Clock (CLK): This control line is driven by the master and regulates the flow of the data
• Slave Select (NSS): This control line allows the master to select or deselect the slave.
• the MOSI line is driven by the output pin TXD
• the MISO line drives the input pin RXD
• the CLK line is driven by the output pin CLK
• the NSS line is driven by the output pin RTS
• the MOSI line drives the input pin RXD
• the MISO line is driven by the output pin TXD
• the CLK line drives the input pin CLK
• the NSS line drives the input pin CTS
into the input of the slave.
of the master.
bits. The master may transmit data at a variety of baud rates. The CLK line cycles once for
each bit that is transmitted.
AT32UC3B
330
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