PIC18F2685-I/SO Microchip Technology, PIC18F2685-I/SO Datasheet - Page 344
![IC PIC MCU FLASH 48KX16 28SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC18F2685-I/SO
Manufacturer Part Number
PIC18F2685-I/SO
Description
IC PIC MCU FLASH 48KX16 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PCM18XT0.pdf
(484 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18F2682-ISP.pdf
(6 pages)
4.PIC18F2682-ISP.pdf
(4 pages)
Specifications of PIC18F2685-I/SO
Program Memory Type
FLASH
Program Memory Size
96KB (48K x 16)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.25 KB
Interface Type
EUSART/I2C/MSSP/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
28
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PCM18XT0 PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F2682-ISP PDF datasheet #3
- PIC18F2682-ISP PDF datasheet #4
- Current page: 344 of 484
- Download datasheet (9Mb)
PIC18F2682/2685/4682/4685
23.15.5
When the PIC18F2682/2685/4682/4685 devices are in
Sleep mode and the bus activity wake-up interrupt is
enabled, an interrupt will be generated and the WAKIF
bit will be set when activity is detected on the CAN bus.
This interrupt causes the PIC18F2682/2685/4682/
4685 devices to exit Sleep mode. The interrupt is reset
by the MCU, clearing the WAKIF bit.
23.15.6
When the error interrupt is enabled, an interrupt is
generated if an overflow condition occurs or if the error
state of the transmitter or receiver has changed. The
error flags in COMSTAT will indicate one of the
following conditions.
23.15.6.1
An overflow condition occurs when the MAB has
assembled a valid received message (the message
meets the criteria of the acceptance filters) and the
receive buffer associated with the filter is not available
for loading of a new message. The associated
RXBnOVFL bit in the COMSTAT register will be set to
indicate the overflow condition. This bit must be cleared
by the MCU.
23.15.6.2
The receive error counter has reached the MCU
warning limit of 96.
DS39761C-page 344
BUS ACTIVITY WAKE-UP
INTERRUPT
ERROR INTERRUPT
Receiver Overflow
Receiver Warning
23.15.6.3
The transmit error counter has reached the MCU
warning limit of 96.
23.15.6.4
The receive error counter has exceeded the error-
passive limit of 127 and the device has gone to
error-passive state.
23.15.6.5
The transmit error counter has exceeded the error-
passive limit of 127 and the device has gone to
error-passive state.
23.15.6.6
The transmit error counter has exceeded 255 and the
device has gone to bus-off state.
23.15.6.7
Interrupts are directly associated with one or more
status flags in the PIR register. Interrupts are pending
as long as one of the flags is set. Once an interrupt flag
is set by the device, the flag can not be reset by the
microcontroller until the interrupt condition is removed.
Transmitter Warning
Receiver Bus Passive
Transmitter Bus Passive
Bus-Off
Interrupt Acknowledge
© 2009 Microchip Technology Inc.
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