PIC17C44-25/PQ Microchip Technology, PIC17C44-25/PQ Datasheet - Page 84
![IC MCU OTP 8KX16 PWM 44-MQFP](/photos/6/59/65984/150-44-pqfp_sml.jpg)
PIC17C44-25/PQ
Manufacturer Part Number
PIC17C44-25/PQ
Description
IC MCU OTP 8KX16 PWM 44-MQFP
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC17C42A-16P.pdf
(241 pages)
3.PIC17C44-16L.pdf
(4 pages)
Specifications of PIC17C44-25/PQ
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
33
Program Memory Size
16KB (8K x 16)
Program Memory Type
OTP
Ram Size
454 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
44-MQFP, 44-PQFP
For Use With
AC164316 - MODULE SKT MPLAB PM3 44MQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC17C44-25/PQ
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC17C4X
FIGURE 13-2: RCSTA REGISTER (ADDRESS: 13h, BANK 0)
DS30412C-page 84
bit7
bit 7:
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
R/W - 0 R/W - 0 R/W - 0 R/W - 0
SPEN
SPEN : Serial Port Enable bit
1 = Configures RA5/RX/DT and RA4/TX/CK pins as serial port pins
0 = Serial port disabled
RX9 : 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
SREN : Single Receive Enable bit
This bit enables the reception of a single byte. After receiving the byte, this bit is automatically cleared.
Synchronous mode:
1 = Enable reception
0 = Disable reception
Note: This bit is ignored in synchronous slave reception.
Asynchronous mode:
Don’t care
CREN : Continuous Receive Enable bit
This bit enables the continuous reception of serial data.
Asynchronous mode:
1 = Enable reception
0 = Disables reception
Synchronous mode:
1 = Enables continuous reception until CREN is cleared (CREN overrides SREN)
0 = Disables continuous reception
Unimplemented : Read as '0'
FERR : Framing Error bit
1 = Framing error (Updated by reading RCREG)
0 = No framing error
OERR : Overrun Error bit
1 = Overrun (Cleared by clearing CREN)
0 = No overrun error
RX9D : 9th bit of receive data (can be the software calculated parity bit)
RX9
SREN
CREN
U - 0
—
FERR
R - 0
OERR
R - 0
RX9D
R - x
bit 0
R = Readable bit
W = Writable bit
-n = Value at POR reset
(x = unknown)
1996 Microchip Technology Inc.
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