ATSAM3S2AA-AU Atmel, ATSAM3S2AA-AU Datasheet - Page 92
ATSAM3S2AA-AU
Manufacturer Part Number
ATSAM3S2AA-AU
Description
IC MCU 32BIT 128KB FLASH 48LQFP
Manufacturer
Atmel
Series
SAM3Sr
Specifications of ATSAM3S2AA-AU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 8x10/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Controller Family/series
ATSAM3S
No. Of I/o's
34
Ram Memory Size
32KB
Cpu Speed
64MHz
No. Of Timers
6
Rohs Compliant
Yes
Processor Series
ATSAM3x
Core
ARM Cortex M3
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3S-EK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATSAM3S2AA-AU
Manufacturer:
AMD
Quantity:
101
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10.12.3
10.12.3.1
10.12.3.2
10.12.3.3
92
SAM3S Preliminary
LDR and STR, register offset
Syntax
Operation
Restrictions
Load and Store with register offset.
where:
op
type
cond
Rt
Rn
Rm
LSL #n
LDR instructions load a register with a value from memory.
STR instructions store a register value into memory.
The memory address to load from or store to is at an offset from the register Rn. The offset is
specified by the register Rm and can be shifted left by up to 3 bits using LSL.
The value to load or store can be a byte, halfword, or word. For load instructions, bytes and half-
words can either be signed or unsigned. See
In these instructions:
When Rt is PC in a word load instruction:
• Rn must not be PC
• Rm must not be SP and must not be PC
• Rt can be SP only for word loads and word stores
• Rt can be PC only for word loads.
• bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this
• if the instruction is conditional, it must be the last instruction in the IT block.
halfword-aligned address
op{type}{cond} Rt, [Rn, Rm {, LSL #n}]
LDR
STR
B
SB
H
SH
-
is one of:
Load Register.
Store Register.
is one of:
unsigned byte, zero extend to 32 bits on loads.
signed byte, sign extend to 32 bits (LDR only).
unsigned halfword, zero extend to 32 bits on loads.
signed halfword, sign extend to 32 bits (LDR only).
omit, for word.
is an optional condition code, see
is the register to load or store.
is the register on which the memory address is based.
is a register containing a value to be used as the offset.
is an optional shift, with n in the range 0 to 3.
“Address alignment” on page
“Conditional execution” on page
83.
6500C–ATARM–8-Feb-11
84.
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