ATSAM3S2AA-AU Atmel, ATSAM3S2AA-AU Datasheet - Page 354
ATSAM3S2AA-AU
Manufacturer Part Number
ATSAM3S2AA-AU
Description
IC MCU 32BIT 128KB FLASH 48LQFP
Manufacturer
Atmel
Series
SAM3Sr
Specifications of ATSAM3S2AA-AU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 8x10/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Controller Family/series
ATSAM3S
No. Of I/o's
34
Ram Memory Size
32KB
Cpu Speed
64MHz
No. Of Timers
6
Rohs Compliant
Yes
Processor Series
ATSAM3x
Core
ARM Cortex M3
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3S-EK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATSAM3S2AA-AU
Manufacturer:
AMD
Quantity:
101
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22.8.2
Name:
Access:
• SLOT_CYCLE: Maximum Number of Allowed Cycles for a Burst
When the SLOT_CYCLE limit is reach for a burst it may be broken by another master trying to access this slave.
This limit has been placed to avoid locking very slow slaves when very long bursts are used.
This limit should not be very small though. An unreasonable small value will break every burst and the Bus Matrix will
spend its time to arbitrate without performing any data transfer. 16 cycles is a reasonable value for SLOT_CYCLE.
• DEFMSTR_TYPE: Default Master Type
0: No Default Master
At the end of current slave access, if no other master request is pending, the slave is disconnected from all masters.
This results in having a one cycle latency for the first access of a burst transfer or for a single access.
1: Last Default Master
At the end of current slave access, if no other master request is pending, the slave stays connected to the last master hav-
ing accessed it.
This results in not having the one cycle latency when the last master re-tries access on the slave again.
2: Fixed Default Master
At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the
number that has been written in the FIXED_DEFMSTR field.
This results in not having the one cycle latency when the fixed master re-tries access on the slave again.
• FIXED_DEFMSTR: Fixed Default Master
This is the number of the Default Master for this slave. Only used if DEFMSTR_TYPE is 2. Specifying the number of a mas-
ter which is not connected to the selected slave is equivalent to setting DEFMSTR_TYPE to 0.
• ARBT: Arbitration Type
0: Round-Robin Arbitration
1: Fixed Priority Arbitration
2: Reserved
3: Reserved
6500C–ATARM–8-Feb-11
31
23
15
–
–
–
7
Bus Matrix Slave Configuration Registers
MATRIX_SCFG0..MATRIX_SCFG4
Read-write
30
22
14
–
–
–
6
29
21
13
–
–
–
5
28
20
12
–
–
4
SLOT_CYCLE
FIXED_DEFMSTR
27
19
11
–
–
3
26
18
10
–
–
2
SAM3S Preliminary
25
17
9
–
1
DEFMSTR_TYPE
ARBT
24
16
8
–
0
354
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