AT91SAM9G10-CU Atmel, AT91SAM9G10-CU Datasheet - Page 21
![IC MCU ARM9 SAMPLING 217CBGA](/photos/12/13/121366/217-lfbga_sml.jpg)
AT91SAM9G10-CU
Manufacturer Part Number
AT91SAM9G10-CU
Description
IC MCU ARM9 SAMPLING 217CBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9G10-CU.pdf
(39 pages)
Specifications of AT91SAM9G10-CU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
266MHz
Connectivity
EBI/EMI, I²C, IrDA, ISI, MMC, SPI, SSC, UART/USART, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
217-LFBGA
Controller Family/series
AT91
No. Of I/o's
96
Ram Memory Size
16KB
Cpu Speed
266MHz
No. Of Timers
1
Rohs Compliant
Yes
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
EBI, SPI, TWI, USART
Maximum Clock Frequency
266 MHz
Number Of Programmable I/os
96
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9G10-EK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM9G10-CU
Manufacturer:
Atmel
Quantity:
1 466
Part Number:
AT91SAM9G10-CU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
9.2
9.3
9.4
9.5
6462AS–ATARM–03-Jun-09
Reset Controller
Shutdown Controller
General-purpose Backup Registers
Clock Generator
Figure 9-2.
• Based on two Power-on-Reset cells
• Status of the last reset
• Controls the internal resets and the NRST pin output
• Shutdown and Wake-up logic:
• Four 32-bit general-purpose backup registers
• Embeds the Low-power 32,768 Hz Slow Clock Oscillator
• Embeds the Main Oscillator
• Embeds Two PLLs
• Provides SLCK, MAINCK, PLLACK and PLLBCK.
– Either cold reset, first reset, soft reset, user reset, watchdog reset, wake-up reset
– Software programmable assertion of the SHDN pin
– Deassertion Programmable on a WKUP pin level change or on alarm
– Provides the permanent Slow Clock to the system
– Oscillator bypass feature
– Supports 3 to 20 MHz crystals
– Outputs 80 to 300 MHz clocks
– Integrates an input divider to increase output accuracy
– 1 MHz minimum input frequency
Clock Generator Block Diagram
XOUT32
PLLRCA
PLLRCB
XIN32
XOUT
XIN
Clock Generator
Management
Slow Clock
Controller
Oscillator
Oscillator
PLL and
Divider A
PLL and
Divider B
Status
Power
Main
Control
Slow Clock
SLCK
Main Clock
MAINCK
PLLA Clock
PLLACK
PLLB Clock
PLLBCK
AT91SAM9G10
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