AT89C51RC2-3CSUM Atmel, AT89C51RC2-3CSUM Datasheet - Page 11

• Manufacturer Part Number: AT89C51RC2-3CSUM
• Description: IC 8051 MCU FLASH 32K 40DIP
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51RC2-3CSUM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 60MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1.25 KB
• Interface Type: SPI/UART
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Cpu Family: AT89
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 60MHz
• Total Internal Ram Size: 1.25KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 40
• Package Type: PDIP
• For Use With: AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCUAT89STK-11 - KIT STARTER FOR AT89C51RX2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 12. Pin Description for 40 - 44 Pin Packages (Continued)
4180E–8051–10/06
Mnemonic
P1.0 - P1.7
XTAL1
XTAL2
P2.0 - P2.7
P3.0 - P3.7
RST
ALE/PROG
21 - 28
10 - 17
DIL
19
18
10
12
13
14
15
16
17
30
11
9
Pin Number
24 - 31
13 - 19
LCC
11,
21
20
11
13
14
15
16
17
18
19
10
33
VQFP44 1.4
18 - 25
7 - 13
15
14
10
11
12
13
27
5,
5
7
8
9
4
Type
O (I)
I/O
I/O
I/O
I/O
I/O
O
O
O
O
I
I
I
I
I
I
Name and Function
CEX4: Capture/Compare External I/O for PCA Module 4
MOSI: SPI Master Output Slave Input line
When SPI is in master mode, MOSI outputs data to the slave peripheral. When SPI
is in slave mode, MOSI receives data from the master controller.
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock
generator circuits.
Crystal 2: Output from the inverting oscillator amplifier
Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, Port 2 pins that are externally pulled low will source current
because of the internal pull-ups. Port 2 emits the high - order address Byte during
fetches from external program memory and during accesses to external data
memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses
strong internal pull-ups emitting 1s. During accesses to external data memory that
use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR. Some
Port 2 pins receive the high order address bits during EPROM programming and
verification:
P2.0 to P2.5 for 16 KB devices
P2.0 to P2.6 for 32KB devices
Port 3: Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, Port 3 pins that are externally pulled low will source current
because of the internal pull-ups. Port 3 also serves the special features of the
80C51 family, as listed below.
RXD (P3.0): Serial input port
TXD (P3.1): Serial output port
INT0 (P3.2): External interrupt 0
INT1 (P3.3): External interrupt 1
T0 (P3.4): Timer 0 external input
T1 (P3.5): Timer 1 external input
WR (P3.6): External data memory write strobe
RD (P3.7): External data memory read strobe
Reset: A high on this pin for two machine cycles while the oscillator is running,
resets the device. An internal diffused resistor to V
only an external capacitor to V
watchdog forces a system reset.
Address Latch Enable/Program Pulse: Output pulse for latching the low Byte of
the address during an access to external memory. In normal operation, ALE is
emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can
be used for external timing or clocking. Note that one ALE pulse is skipped during
each access to external data memory. This pin is also the program pulse input
(PROG) during Flash programming. ALE can be disabled by setting SFR’s AUXR. 0
bit. With this bit set, ALE will be inactive during internal fetches.
CC
. This pin is an output when the hardware
AT89C51RB2/RC2
SS
permits a power-on reset using
11