DSPIC30F5015-30I/PT Microchip Technology, DSPIC30F5015-30I/PT Datasheet - Page 127

• Manufacturer Part Number: DSPIC30F5015-30I/PT
• Description: IC DSPIC MCU/DSP 66K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F5015-30I/PT

• Program Memory Type: FLASH
• Program Memory Size: 66KB (22K x 24)
• Package / Case: 64-TFQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 52
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 30 MHz
• Number Of Programmable I/os: 52
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM330011
• Minimum Operating Temperature: - 40 C
• Package: 64TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPAC30F008 - MODULE SKT FOR DSPIC30F 64TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F501530IPT

19.3
The CAN module can operate in one of several operation
modes selected by the user. These modes include:
• Initialization Mode
• Disable Mode
• Normal Operation Mode
• Listen-Only Mode
• Loopback Mode
• Error Recognition Mode
Modes are requested by setting the REQOP<2:0>
bits (CiCTRL<10:8>).
acknowledged by monitoring the OPMODE<2:0> bits
(CiCTRL<7:5>). The module will not change the mode
and the OPMODE bits until a change in mode is
acceptable, generally during bus idle time which is
defined as at least 11 consecutive recessive bits.
19.3.1
In the Initialization mode, the module will not transmit or
receive. The error counters are cleared and the inter-
rupt flags remain unchanged. The programmer will
have access to Configuration registers that are access
restricted in other modes. The module will protect the
user from accidentally violating the CAN protocol
through programming errors. All registers which control
the configuration of the module can not be modified
while the module is on-line. The CAN module will not
be allowed to enter the Configuration mode while a
transmission is taking place. The Configuration mode
serves as a lock to protect the following registers:
• All Module Control Registers
• Baud Rate and Interrupt Configuration Registers
• Bus Timing Registers
• Identifier Acceptance Filter Registers
• Identifier Acceptance Mask Registers
19.3.2
In Disable mode, the module will not transmit or
receive. The module has the ability to set the WAKIF bit
due to bus activity, however any pending interrupts will
remain and the error counters will retain their value.
If the REQOP<2:0> bits (CiCTRL<10:8>) = 001, the
module will enter the Module Disable mode. If the mod-
ule is active, the module will wait for 11 recessive bits
on the CAN bus, detect that condition as an idle bus,
then accept the module disable command. When the
OPMODE<2:0> bits (CiCTRL<7:5>) = 001, that indi-
cates whether the module successfully went into Mod-
ule Disable mode. The I/O pins will revert to normal I/O
function when the module is in the Module Disable
mode.
© 2008 Microchip Technology Inc.
Modes of Operation
INITIALIZATION MODE
DISABLE MODE
Entry
into
a
mode
is
The module can be programmed to apply a low-pass
filter function to the CiRX input line while the module or
the CPU is in Sleep mode. The WAKFIL bit
(CiCFG2<14>) enables or disables the filter.
19.3.3
Normal
REQOP<2:0> = 000. In this mode, the module is
activated, the I/O pins will assume the CAN bus
functions. The module will transmit and receive CAN
bus messages via the CxTX and CxRX pins.
19.3.4
If the Listen-Only mode is activated, the module on the
CAN bus is passive. The transmitter buffers revert to
the Port I/O function. The receive pins remain inputs.
For the receiver, no error flags or Acknowledge signals
are sent. The error counters are deactivated in this
state. The Listen-Only mode can be used for detecting
the baud rate on the CAN bus. To use this, it is neces-
sary that there are at least two further nodes that
communicate with each other.
19.3.5
The module can be set to ignore all errors and receive
any message. The Error Recognition mode is activated
by setting the RXM<1:0> bits (CiRXnCON<6:5>) regis-
ters to ‘11’. In this mode, the data which is in the
message assembly buffer until the time an error
occurred, is copied in the receive buffer and can be
read via the CPU interface.
19.3.6
If the Loopback mode is activated, the module will con-
nect the internal transmit signal to the internal receive
signal at the module boundary. The transmit and
receive pins revert to their port I/O function.
Note:
dsPIC30F5015/5016
Operating
Typically, if the CAN module is allowed to
transmit in a particular mode of operation
and a transmission is requested immedi-
ately after the CAN module has been
placed in that mode of operation, the mod-
ule waits for 11 consecutive recessive bits
on the bus before starting transmission. If
the user switches to Disable mode within
this 11-bit period, then this transmission is
aborted and the corresponding TXABT bit
is set and TXREQ bit is cleared.
NORMAL OPERATION MODE
LISTEN-ONLY MODE
ERROR RECOGNITION MODE
LOOPBACK MODE
mode
is
DS70149D-page 127
selected
when