AT90CAN64-16MU Atmel, AT90CAN64-16MU Datasheet - Page 199
AT90CAN64-16MU
Manufacturer Part Number
AT90CAN64-16MU
Description
IC MCU AVR 64K FLASH 64-QFN
Manufacturer
Atmel
Series
AVR® 90CANr
Specifications of AT90CAN64-16MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
Processor Series
AT90CANx
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
53
Number Of Timers
2
Operating Supply Voltage
0.5 V to 0.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATDVK90CAN1, ATADAPCAN01
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT90CAN64-16MU
Manufacturer:
ATMEL
Quantity:
210
Part Number:
AT90CAN64-16MU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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17.11.9
17.11.10 USART1 Baud Rate Registers – UBRR1L and UBRR1H
7679H–CAN–08/08
USART0 Baud Rate Registers – UBRR0L and UBRR0H
• Bit 2:1 – UCSZn1:0: Character Size
The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits
(Character SiZe) in a frame the Receiver and Transmitter use.
Table 17-7.
• Bit 0 – UCPOLn: Clock Polarity
This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is
used. The UCPOLn bit sets the relationship between data output change and data input sample,
and the synchronous clock (XCKn).
Table 17-8.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
UCPOLn
UCSZn2
0
1
0
0
0
0
1
1
1
1
UCSZn Bits Settings
UCPOLn Bit Settings
Transmitted Data Changed
(Output of TxDn Pin)
Rising XCK Edge
Falling XCK Edge
R/W
R/W
15
15
R
R
–
7
0
0
–
7
0
0
R/W
R/W
14
14
R
R
–
6
0
0
–
6
0
0
UCSZn1
0
0
1
1
0
0
1
1
R/W
R/W
13
13
R
R
–
5
0
0
–
5
0
0
R/W
R/W
12
12
–
4
R
0
0
–
4
R
0
0
UBRR0[7:0]
UBRR1[7:0]
UCSZn0
R/W
R/W
R/W
R/W
11
11
3
0
0
3
0
0
0
1
0
1
0
1
0
1
R/W
R/W
R/W
R/W
10
10
UBRR0[11:8]
UBRR1[11:8]
2
0
0
2
0
0
Received Data Sampled
(Input on RxDn Pin)
Falling XCK Edge
Rising XCK Edge
AT90CAN32/64/128
Character Size
5-bit
6-bit
7-bit
8-bit
Reserved
Reserved
Reserved
9-bit
R/W
R/W
R/W
R/W
9
1
0
0
9
1
0
0
R/W
R/W
R/W
R/W
8
0
0
0
8
0
0
0
UBRR0H
UBRR1H
UBRR0L
UBRR1L
199
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