AT90CAN64-16MU Atmel, AT90CAN64-16MU Datasheet - Page 110

• Manufacturer Part Number: AT90CAN64-16MU
• Description: IC MCU AVR 64K FLASH 64-QFN
• Manufacturer: Atmel
• Series: AVR® 90CANr

Specifications of AT90CAN64-16MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Processor Series: AT90CANx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 2
• Operating Supply Voltage: 0.5 V to 0.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATDVK90CAN1, ATADAPCAN01
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

110
AT90CAN32/64/128
• Bit 6, 3 – WGM01:0: Waveform Generation Mode
These bits control the counting sequence of the counter, the source for the maximum (TOP)
counter value, and what type of waveform generation to be used. Modes of operation supported
by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and
two types of Pulse Width Modulation (PWM) modes. See
on page
Table 12-1.
Note:
• Bit 5:4 – COM01:0: Compare Match Output Mode
These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0
bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A pin
must be set in order to enable the output driver.
When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the
WGM01:0 bit setting.
are set to a normal or CTC mode (non-PWM).
Table 12-2.
Table 12-3
mode.
Table 12-3.
Mode
COM0A1
COM0A1
0
1
2
3
0
0
1
1
0
0
1
1
1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 definitions.
104.
WGM01
(CTC0)
However, the functionality and location of these bits are compatible with previous versions of
the timer.
shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM
0
0
1
1
Waveform Generation Mode Bit Description
Compare Output Mode, non-PWM Mode
Compare Output Mode, Fast PWM Mode
COM0A0
COM0A0
0
1
0
1
0
1
0
1
Table 12-2
WGM00
(PWM0)
0
1
0
1
Description
Normal port operation, OC0A disconnected.
Toggle OC0A on compare match
Clear OC0A on compare match
Set OC0A on compare match
Description
Normal port operation, OC0A disconnected.
Reserved
Clear OC0A on compare match.
Set OC0A at TOP
Set OC0A on compare match.
Clear OC0A at TOP
Timer/Counter
Mode of Operation
Normal
PWM, Phase Correct
CTC
Fast PWM
shows the COM0A1:0 bit functionality when the WGM01:0 bits
(1)
TOP
0xFF
0xFF
OCR0A
0xFF
Table 12-1
(1)
Update of
OCR0A at
Immediate
TOP
Immediate
TOP
and
“Modes of Operation”
TOV0 Flag
Set on
MAX
BOTTOM
MAX
MAX
7679H–CAN–08/08