AT90USB646-AU Atmel, AT90USB646-AU Datasheet - Page 307
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AT90USB646-AU
Manufacturer Part Number
AT90USB646-AU
Description
MCU AVR 64K FLASH 16MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® 90USBr
Specifications of AT90USB646-AU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART, USB, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Controller Family/series
AVR USB
No. Of I/o's
48
Eeprom Memory Size
2KB
Ram Memory Size
4KB
Cpu Speed
20MHz
Rohs Compliant
Yes
Processor Series
AT90USBx
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
48
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATSTK525, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
64TQFP
Device Core
AVR
Family Name
AT90
Maximum Speed
20 MHz
Operating Supply Voltage
3.3|5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT90USB646-AU
Manufacturer:
MOT
Quantity:
1 100
Part Number:
AT90USB646-AU
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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AT90USB64/128
Set by hardware when a NAK has been received on the current bank of the Pipe. This triggers
an interrupt if the NAKEDE bit is set in the UPIENX register.
Shall be clear to handshake the interrupt. Setting by software has no effect.
• 5 - RWAL - Read/Write Allowed
OUT Pipe:
Set by hardware when the firmware can write a new data into the Pipe FIFO.
Cleared by hardware when the current Pipe FIFO is full.
IN Pipe:
Set by hardware when the firmware can read a new data into the Pipe FIFO.
Cleared by hardware when the current Pipe FIFO is empty.
This bit is also cleared by hardware when the RXSTALL or the PERR bit is set
• 4 - PERRI -PIPE Error
Set by hardware when an error occurs on the current bank of the Pipe. This triggers an interrupt
if the PERRE bit is set in the UPIENX register. Refers to the UPERRX register to determine the
source of the error.
Automatically cleared by hardware when the error source bit is cleared.
• 3 - TXSTPI - SETUP Bank ready
Set by hardware when the current SETUP bank is free and can be filled. This triggers an inter-
rupt if the TXSTPE bit is set in the UPIENX register.
Shall be cleared to handshake the interrupt. Setting by software has no effect.
• 2 - TXOUTI -OUT Bank ready
Set by hardware when the current OUT bank is free and can be filled. This triggers an interrupt if
the TXOUTE bit is set in the UPIENX register.
Shall be cleared to handshake the interrupt. Setting by software has no effect.
• 1 - RXSTALLI / CRCERR - STALL Received / Isochronous CRC Error
Set by hardware when a STALL handshake has been received on the current bank of the Pipe.
The Pipe is automatically frozen. This triggers an interrupt if the RXSTALLE bit is set in the UPI-
ENX register.
Shall be cleared to handshake the interrupt. Setting by software has no effect.
For Isochronous Pipe:
Set by hardware when a CRC error occurs on the current bank of the Pipe. This triggers an inter-
rupt if the TXSTPE bit is set in the UPIENX register.
Shall be cleared to handshake the interrupt. Setting by software has no effect.
• 0 - RXINI - IN Data received
Set by hardware when a new USB message is stored in the current bank of the Pipe. This trig-
gers an interrupt if the RXINE bit is set in the UPIENX register.
Shall be cleared to handshake the interrupt. Setting by software has no effect.
307
7593K–AVR–11/09
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