AT32UC3B0512-Z2UT Atmel, AT32UC3B0512-Z2UT Datasheet - Page 681
AT32UC3B0512-Z2UT
Manufacturer Part Number
AT32UC3B0512-Z2UT
Description
IC MCU AVR32 512K FLASH 64QFN
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.AT32UC3B1512-Z1UT.pdf
(692 pages)
Specifications of AT32UC3B0512-Z2UT
Core Processor
AVR
Core Size
32-Bit
Speed
60MHz
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
44
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3B0512-Z2UT
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ATMEL
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- Processor and Architecture
1. Local Busto fast GPIO not available on silicon Rev B
2. Memory Protection Unit (MPU) is non functional
3. Bus error should be masked in Debug mode
4. Read Modify Write (RMW) instructions on data outside the internal RAM does not
5. Need two NOPs instruction after instructions masking interrupts
6. Clock connection table on Rev B
Figure 31-1. Timer/Counter clock connections on RevB
7. Spurious interrupt may corrupt core SR mode to exception
Source
Internal
External
Local bus is only available for silicon RevE and later.
Fix/Workaround
Memory Protection Unit (MPU) is non functional.
Fix/Workaround
Do not use the MPU.
If a bus error occurs during debug mode, the processor will not respond to debug com-
mands through the DINST register.
Fix/Workaround
A reset of the device will make the CPU respond to debug commands again.
work
Read Modify Write (RMW) instructions on data outside the internal RAM does not work.
Fix/Workaround
Do not perform RMW instructions on data outside the internal RAM.
The instructions following in the pipeline the instruction masking the interrupt through SR
may behave abnormally.
Fix/Workaround
Place two NOPs instructions after each SSRF or MTSR instruction setting IxM or GM in SR
Here is the table of Rev B
If the rules listed in the chapter `Masking interrupt requests in peripheral modules' of the
AVR32UC Technical Reference Manual are not followed, a spurious interrupt may occur. An
Do not use if silicon revison older than F.
Name
TIMER_CLOCK1
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
XC0
XC1
XC2
Connection
32KHz Oscillator
PBA Clock / 4
PBA Clock / 8
PBA Clock / 16
PBA Clock / 32
AT32UC3B
681
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