AT32UC3B0512-Z2UT Atmel, AT32UC3B0512-Z2UT Datasheet - Page 654
AT32UC3B0512-Z2UT
Manufacturer Part Number
AT32UC3B0512-Z2UT
Description
IC MCU AVR32 512K FLASH 64QFN
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.AT32UC3B1512-Z1UT.pdf
(692 pages)
Specifications of AT32UC3B0512-Z2UT
Core Processor
AVR
Core Size
32-Bit
Speed
60MHz
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
44
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3B0512-Z2UT
Manufacturer:
ATMEL
Quantity:
2 010
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32059K–03/2011
- Processor and Architecture
- Flash
- USART
1. LDM instruction with PC in the register list and without ++ increments Rp
2. RETE instruction does not clear SREG[L] from interrupts
3. Privilege violation when using interrupts in application mode with protected system
1. Reset vector is 80000020h rather than 80000000h
1. ISO7816 info register US_NER cannot be read
2. ISO7816 Mode T1: RX impossible after any TX
3. The RTS output does not function correctly in hardware handshaking mode
For LDM with PC in the register list: the instruction behaves as if the ++ field is always set, ie
the pointer is always updated. This happens even if the ++ field is cleared. Specifically, the
increment of the pointer is done in parallel with the testing of R12.
Fix/Workaround
None.
The RETE instruction clears SREG[L] as expected from exceptions.
Fix/Workaround
When using the STCOND instruction, clear SREG[L] in the stacked value of SR before
returning from interrupts with RETE.
stack
If the system stack is protected by the MPU and an interrupt occurs in application mode, an
MPU DTLB exception will occur.
Fix/Workaround
Make a DTLB Protection (Write) exception handler which permits the interrupt request to be
handled in privileged mode.
Reset vector is 80000020h rather than 80000000h.
Fix/Workaround
The flash program code must start at the address 80000020h. The flash memory range
80000000h-80000020h must be programmed with 00000000h.
The NER register always returns zero.
Fix/Workaround
None.
RX impossible after any TX.
Fix/Workaround
SOFT_RESET on RX+ Config US_MR + Config_US_CR.
The RTS signal is not generated properly when the USART receives data in hardware hand-
shaking mode. When the Peripheral DMA receive buffer becomes full, the RTS output
should go high, but it will stay low.
Fix/Workaround
Do not use the hardware handshaking mode of the USART. If it is necessary to drive the
RTS output high when the Peripheral DMA receive buffer becomes full, use the normal
mode of the USART. Configure the Peripheral DMA Controller to signal an interrupt when
the receive buffer is full. In the interrupt handler code, write a one to the RTSDIS bit in the
USART Control Register (CR). This will drive the RTS output high. After the next DMA trans-
AT32UC3B
654
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