DSPIC33FJ64MC710-E/PF Microchip Technology, DSPIC33FJ64MC710-E/PF Datasheet - Page 11
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DSPIC33FJ64MC710-E/PF
Manufacturer Part Number
DSPIC33FJ64MC710-E/PF
Description
IC DSPIC MCU/DSP 64K 100TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.MA330013.pdf
(370 pages)
2.PIC24HJ12GP201-ISO.pdf
(84 pages)
3.DSPIC33FJ64MC506-IPT.pdf
(340 pages)
4.DSPIC33FJ64MC506-IPT.pdf
(30 pages)
Specifications of DSPIC33FJ64MC710-E/PF
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 24x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
100-TQFP, 100-VQFP
For Use With
MA330013 - MODULE PLUG-IN DSPIC33 100TQFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164323 - MODULE SKT FOR 100TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
9. Module: SPI
10. Module: ECAN
11. Module: ECAN
© 2010 Microchip Technology Inc.
The SMP bit (SPIxCON1<9>, where x = 1 or 2)
does not have any effect when the SPI module is
configured for a 1:1 prescale factor in Master
mode. In this mode, whether the SMP bit is set or
cleared, the data is always sampled at the end of
data output time.
Work around
If sampling at the middle of data output time is
required, then configure the SPI module to use a
clock prescale factor other than 1:1, using the
PPRE<1:0>
SPIxCON1 register.
Affected Silicon Revisions
If any buffers other than Buffer 0 are enabled as
transmit buffers (i.e., if the TXEN bits other than
TXEN0 are set to ‘1’), incorrect ID and data
transmissions will occur intermittently.
Work around
Enable only Buffer 0 for transmission.
Affected Silicon Revisions
Under specific conditions, the first five bits of a
transmitted identifier may not match the value in
the transmit buffer, SID. If the ECAN module
detects a Start-of-Frame (SOF) in the third bit of
interframe space, and if a message to be
transmitted is pending, the first five bits of the
transmitted identifier may be corrupted.
Work around
None.
Affected Silicon Revisions
A2
A2
A2
X
X
X
A3
A3
A3
X
X
X
A4
A4
A4
and
X
X
X
SPRE<2:0>
bits
in
the
12. Module: ECAN
13. Module: I
14. Module: ADC
The ECAN module (ECAN1 or ECAN2) does not
function correctly in Loopback mode.
Work around
Do not use Loopback mode.
Affected Silicon Revisions
The Bus Collision Status bit (BCL) is not set when
a bus collision occurs during a Restart or Stop
event. However, the BCL bit is set when a bus
collision occurs during a Start event.
Work around
None.
Affected Silicon Revisions
ADC event triggers from the INT0 pin will not
wake-up the device from Sleep or Idle mode if the
SMPI bits are non-zero. That is, if the ADC is
configured to generate an interrupt after a certain
number of INT0 triggered conversions, the ADC
conversions will not be triggered and the device
will remain in Sleep. The ADC will perform
conversions and wake-up the device only when it
is configured to generate an interrupt after each
INT0 triggered conversion (SMPI<3:0> = 0000).
Work around
None. If an ADC event trigger from the INT0 pin is
required, initialize SMPI<3:0> to ‘0000’ (interrupt
on every conversion).
Affected Silicon Revisions
A2
A2
A2
X
X
X
A3
A3
A3
X
X
X
2
C
A4
A4
A4
X
X
X
DS80447D-page 11