PIC16LF77-I/L Microchip Technology, PIC16LF77-I/L Datasheet - Page 69
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PIC16LF77-I/L
Manufacturer Part Number
PIC16LF77-I/L
Description
IC PIC MCU FLASH 8KX14 44PLCC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Specifications of PIC16LF77-I/L
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
PIC16LF77I/L
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16LF77-I/L
Manufacturer:
Microchip Technology
Quantity:
10 000
FIGURE 9-6:
9.3.1.3
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit, and pin RC3/SCK/SCL is held
low. The transmit data must be loaded into the
SSPBUF register, which also loads the SSPSR regis-
ter. Then, pin RC3/SCK/SCL should be enabled by set-
ting bit CKP (SSPCON<4>). The master must monitor
the SCL pin prior to asserting another clock pulse. The
slave devices may be holding off the master by stretch-
ing the clock. The eight data bits are shifted out on the
falling edge of the SCL input. This ensures that the
SDA signal is valid during the SCL high time (Figure 9-7).
FIGURE 9-7:
2002 Microchip Technology Inc.
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
CKP (SSPCON<4>)
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
S
S
A7 A6 A5 A4 A3 A2 A1
1
Transmission
A7
2
1
Data in
sampled
Receiving Address
3
A6
2
I
I
4
2
2
C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
A5
Receiving Address
3
5
A4
4
6
7
A3
R/W=0
5
8
A2
6
ACK
9
A1
7
D7
1
R/W = 1
D6
2
8
SSPBUF register is read
Receiving Data
D5
3
Cleared in software
9
ACK
D4
Bit SSPOV is set because the SSPBUF register is still full.
responds to SSPIF
4
SCL held low
while CPU
D3
5
D2
6
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF must be cleared in software, and
the SSPSTAT register is used to determine the status
of the byte. Flag bit SSPIF is set on the falling edge of
the ninth clock pulse.
As a slave-transmitter, the ACK pulse from the master-
receiver is latched on the rising edge of the ninth SCL
input pulse. If the SDA line was high (not ACK), then
the data transfer is complete. When the ACK is latched
by the slave, the slave logic is reset (resets SSPSTAT
register) and the slave then monitors for another occur-
rence of the START bit. If the SDA line was low (ACK),
the transmit data must be loaded into the SSPBUF reg-
ister, which also loads the SSPSR register. Then pin
RC3/SCK/SCL should be enabled by setting bit CKP.
D1
7
D7
D0
1
SSPBUF is written in software
8
ACK
9
D6
2
Cleared in software
Set bit after writing to SSPBUF
(the SSPBUF must be written to
before the CKP bit can be set)
D7
1
D5
3
D6
2
D4
4
D5
Receiving Data
3
Transmitting Data
D3
D4
4
5
ACK is not sent.
D3
5
D2
6
PIC16F7X
D2
6
From SSP Interrupt
Service Routine
D1
7
D1
7
D0
8
D0
DS30325B-page 67
8
ACK
ACK
9
9
Bus Master
terminates
transfer
P
P