AT89C51RC2-SLRUM Atmel, AT89C51RC2-SLRUM Datasheet - Page 49
![IC 8051 MCU 32K FLASH 44-PLCC](/photos/6/70/67043/453-44-plcc_sml.jpg)
AT89C51RC2-SLRUM
Manufacturer Part Number
AT89C51RC2-SLRUM
Description
IC 8051 MCU 32K FLASH 44-PLCC
Manufacturer
Atmel
Series
89Cr
Datasheet
1.AT89C51RB2-RLTIL.pdf
(127 pages)
Specifications of AT89C51RC2-SLRUM
Core Processor
8051
Core Size
8-Bit
Speed
60MHz
Connectivity
SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
For Use With
AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCUAT89STK-11 - KIT STARTER FOR AT89C51RX2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Other names
AT89C51RC2-SLRUMTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT89C51RC2-SLRUM
Manufacturer:
Atmel
Quantity:
500
4180E–8051–10/06
Table 33. SCON Register
SCON - Serial Control Register (98h)
Reset Value = 0000 0000b
Bit addressable
FE/SM0
Number
7
Bit
7
6
5
4
3
2
1
0
SM1
Mnemonic
6
REN
SM0
SM1
SM2
RB8
TB8
Bit
FE
TI
RI
SM2
5
Description
Framing Error bit (SMOD0=1)
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
SMOD0 must be set to enable access to the FE bit.
Serial port Mode bit 0
Refer to SM1 for serial port mode selection.
SMOD0 must be cleared to enable access to the SM0 bit.
Serial port Mode bit 1
SM0
0
0
1
1
Serial port Mode 2 bit / Multiprocessor Communication Enable bit
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and
eventually mode 1.This bit should be cleared in mode 0.
Reception Enable bit
Clear to disable serial reception.
Set to enable serial reception.
Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
Receiver Bit 8 / Ninth bit received in modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not
used.
Transmit Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning
of the stop bit in the other modes.
Receive Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 18.
and Figure 19. in the other modes.
SM1
0
1
0
1
REN
4
Mode
Shift Register F
8-bit UART
9-bit UART
9-bit UART
TB8
3
AT89C51RB2/RC2
Baud Rate
Variable
F
Variable
XTAL
XTAL
/12 (or F
/64 or F
RB8
2
XTAL
XTAL
/32
/6 in mode X2)
1
TI
RI
0
49