ATMEGA64L-8MQR Atmel, ATMEGA64L-8MQR Datasheet - Page 225
ATMEGA64L-8MQR
Manufacturer Part Number
ATMEGA64L-8MQR
Description
MCU AVR 64KB FLASH 8MHZ 64QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA64L-8MQR
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Combining Several
TWI Modes
Multi-master
Systems and
Arbitration
2490Q–AVR–06/10
In some cases, several TWI modes must be combined in order to complete the desired action.
Consider for example reading data from a serial EEPROM. Typically, such a transfer involves
the following steps:
1. The transfer must be initiated.
2. The EEPROM must be instructed what location should be read.
3. The reading must be performed.
4. The transfer must be finished.
Note that data is transmitted both from Master to Slave and vice versa. The Master must instruct
the slave what location it wants to read, requiring the use of the MT mode. Subsequently, data
must be read from the slave, implying the use of the MR mode. Thus, the transfer direction must
be changed. The Master must keep control of the bus during all these steps, and the steps
should be carried out as an atomic operation. If this principle is violated in a multimaster system,
another master can alter the data pointer in the EEPROM between steps 2 and 3, and the mas-
ter will read the wrong data location. Such a change in transfer direction is accomplished by
transmitting a REPEATED START between the transmission of the address byte and reception
of the data. After a REPEATED START, the master keeps ownership of the bus. The following
figure shows the flow in this transfer.
Figure 104. Combining Several TWI Modes to Access a Serial EEPROM
If multiple masters are connected to the same bus, transmissions may be initiated simultane-
ously by one or more of them. The TWI standard ensures that such situations are handled in
such a way that one of the masters will be allowed to proceed with the transfer, and that no data
will be lost in the process. An example of an arbitration situation is depicted below, where two
masters are trying to transmit data to a slave receiver.
Figure 105. An Arbitration Example
Several different scenarios may arise during arbitration, as described below:
S
SDA
SCL
S = START
Transmitted from master to slave
SLA+W
TRANSMITTER
Device 1
MASTER
A
TRANSMITTER
Device 2
MASTER
Master Transmitter
ADDRESS
Device 3
RECEIVER
SLAVE
A
Rs = REPEATED START
Rs
Transmitted from slave to master
........
SLA+R
Device n
V
CC
A
ATmega64(L)
Master Receiver
R1
DATA
R2
P = STOP
A
P
225
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