AT89C51RE2-SLRUM Atmel, AT89C51RE2-SLRUM Datasheet - Page 157
AT89C51RE2-SLRUM
Manufacturer Part Number
AT89C51RE2-SLRUM
Description
MCU 8051 128K FLASH 44-PLCC
Manufacturer
Atmel
Series
89Cr
Datasheet
1.AT89C51RE2-SLSUM.pdf
(187 pages)
Specifications of AT89C51RE2-SLRUM
Core Processor
8051
Core Size
8-Bit
Speed
60MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
34
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
UART, SPI
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
34
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
AT89OCD-01
For Use With
AT89STK-11 - KIT STARTER FOR AT89C51RX2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT89C51RE2-SLRUM
Manufacturer:
Atmel
Quantity:
759
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Registers
Serial Peripheral
Control Register
(SPCON)
7663E–8051–10/08
Figure 65. SPI Interrupt Requests Generation
Three registers in the SPI module provide control, status and data storage functions. These reg-
isters are describe in the following paragraphs.
•
•
•
•
•
•
Table 115 describes this register and explains the use of each bit
Table 115. SPCON Register
SPCON - Serial Peripheral Control Register (0D4H)
Bit Number
SPR2
The Serial Peripheral Control Register does the following:
Selects one of the Master clock rates
Configure the SPI Module as Master or Slave
Selects serial clock polarity and phase
Enables the SPI Module
Frees the SS pin for a general-purpose
7
7
6
5
4
SPEN
6
Bit Mnemonic
MODFIE
SPTEIE
MODF
SPTE
SPIF
SSDIS
MSTR
SPR2
SPEN
SSDIS
5
Description
Serial Peripheral Rate 2
Bit with SPR1 and SPR0 define the clock rate (See bits SPR1 and SPR0 for
detail).
Serial Peripheral Enable
Cleared to disable the SPI interface (internal reset of the SPI).
Set to enable the SPI interface.
SS Disable
Cleared to enable SS in both Master and Slave modes.
Set to disable SS in both Master and Slave modes. In Slave mode, this bit
has no effect if CPHA =’0’. When SSDIS is set, no MODF interrupt request
is generated
Serial Peripheral Master
Cleared to configure the SPI as a Slave.
Set to configure the SPI as a Master.
MSTR
4
.
CPOL
3
CPHA
CPU Interrupt Request
2
SPI
AT89C51RE2
SPR1
1
SPR0
0
157
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