AT89C51RE2-SLRUM Atmel, AT89C51RE2-SLRUM Datasheet - Page 109

• Manufacturer Part Number: AT89C51RE2-SLRUM
• Description: MCU 8051 128K FLASH 44-PLCC
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51RE2-SLRUM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 60MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: UART, SPI
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89OCD-01
• For Use With: AT89STK-11 - KIT STARTER FOR AT89C51RX2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Interrupt
System
Figure 44. Interrupt Control System
7663E–8051–10/08
RI_1
TI_1
TWI IT
SPI IT
EXF2
KBD IT
INT0
INT1
PCA IT
TF0
TF1
TF2
RI
TI
Individual Enable
The AT89C51RE2 has a total of 10 interrupt vectors: two external interrupts (INT0 and INT1),
three timer interrupts (timers 0, 1 and 2), two serial ports interrupts, SPI interrupt, Keyboard
interrupt and the PCA global interrupt. These interrupts are shown in Figure 44.
Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit
in the Interrupt Enable register (Table 84 and Table 82). This register also contains a global dis-
able bit, which must be cleared to disable all interrupts at once.
Each interrupt source can also be individually programmed to one out of four priority levels by
setting or clearing a bit in the Interrupt Priority register (Table 85) and in the Interrupt Priority
High register (Table 83 and Table 84) shows the bit values and priority levels associated with
each combination.
IE0
IE1
IPH, IPL
Global Disable
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
High priority
interrupt
AT89C51RE2
Interrupt
polling
sequence, decreasing from
high to low priority
Low priority
interrupt
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