PIC18F452-E/P Microchip Technology, PIC18F452-E/P Datasheet - Page 226
![IC MCU CMOS 40MHZ 16K FLSH 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18F452-E/P
Manufacturer Part Number
PIC18F452-E/P
Description
IC MCU CMOS 40MHZ 16K FLSH 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F242-ISO.pdf
(332 pages)
3.PIC18F242-ISO.pdf
(14 pages)
4.PIC18F242-ISO.pdf
(16 pages)
5.PIC18F242-ISO.pdf
(16 pages)
6.PIC18F242-ISO.pdf
(14 pages)
7.PIC18LF242-ISO.pdf
(36 pages)
8.PIC18F452-EP.pdf
(332 pages)
Specifications of PIC18F452-E/P
Program Memory Type
FLASH
Program Memory Size
32KB (16K x 16)
Package / Case
40-DIP (0.600", 15.24mm)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
34
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1.5 KB
Interface Type
MSSP/SPI/I2C/PSP/USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
34
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163022
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
40PDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
ACICE0206 - ADAPTER MPLABICE 40P 600 MIL
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F452-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18F242-ISO PDF datasheet #2
- PIC18F242-ISO PDF datasheet #3
- PIC18F242-ISO PDF datasheet #4
- PIC18F242-ISO PDF datasheet #5
- PIC18F242-ISO PDF datasheet #6
- PIC18LF242-ISO PDF datasheet #7
- PIC18F452-EP PDF datasheet #8
- Current page: 226 of 332
- Download datasheet (6Mb)
PIC18FXX2
BTFSC
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39564C-page 224
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
PC
If FLAG<1>
If FLAG<1>
No
No
No
Q1
Q1
Q1
PC
PC
Bit Test File, Skip if Clear
[ label ] BTFSC f,b[,a]
0
0
a
skip if (f<b>) = 0
None
If bit 'b' in register ’f' is 0, then the
next instruction is skipped.
If bit 'b' is 0, then the next instruction
fetched during the current instruction
execution is discarded, and a NOP is
executed instead, making this a two-
cycle instruction. If ‘a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (default).
1
1(2)
Note: 3 cycles if skip and followed
HERE
FALSE
TRUE
register 'f'
operation
operation
operation
Read
1011
No
No
No
Q2
Q2
Q2
=
=
=
=
=
f
b
[0,1]
255
7
address (HERE)
0;
address (TRUE)
1;
address (FALSE)
by a 2-word instruction.
BTFSC
:
:
Process Data
bbba
operation
operation
operation
No
No
No
Q3
Q3
Q3
FLAG, 1, 0
ffff
operation
operation
operation
operation
No
No
No
No
Q4
Q4
Q4
ffff
BTFSS
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
PC
If FLAG<1>
If FLAG<1>
No
No
No
Q1
Q1
Q1
PC
PC
Bit Test File, Skip if Set
[ label ] BTFSS f,b[,a]
0
0
a
skip if (f<b>) = 1
None
If bit 'b' in register 'f' is 1, then the
next instruction is skipped.
If bit 'b' is 1, then the next instruction
fetched during the current instruc-
tion execution, is discarded and a
NOP is executed instead, making this
a two-cycle instruction. If ‘a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (default).
1
1(2)
Note:
HERE
FALSE
TRUE
register 'f'
operation
operation
operation
Read
1010
No
No
No
Q2
Q2
Q2
=
=
=
=
=
f
b
[0,1]
© 2006 Microchip Technology Inc.
255
7
address (HERE)
0;
address (FALSE)
1;
address (TRUE)
3 cycles if skip and followed
by a 2-word instruction.
BTFSS
:
:
Process Data
bbba
operation
operation
operation
No
No
No
Q3
Q3
Q3
FLAG, 1, 0
ffff
operation
operation
operation
operation
No
No
No
No
Q4
Q4
Q4
ffff
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