PIC18F452-E/P Microchip Technology, PIC18F452-E/P Datasheet - Page 180
![IC MCU CMOS 40MHZ 16K FLSH 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18F452-E/P
Manufacturer Part Number
PIC18F452-E/P
Description
IC MCU CMOS 40MHZ 16K FLSH 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F242-ISO.pdf
(332 pages)
3.PIC18F242-ISO.pdf
(14 pages)
4.PIC18F242-ISO.pdf
(16 pages)
5.PIC18F242-ISO.pdf
(16 pages)
6.PIC18F242-ISO.pdf
(14 pages)
7.PIC18LF242-ISO.pdf
(36 pages)
8.PIC18F452-EP.pdf
(332 pages)
Specifications of PIC18F452-E/P
Program Memory Type
FLASH
Program Memory Size
32KB (16K x 16)
Package / Case
40-DIP (0.600", 15.24mm)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
34
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1.5 KB
Interface Type
MSSP/SPI/I2C/PSP/USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
34
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163022
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
40PDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
ACICE0206 - ADAPTER MPLABICE 40P 600 MIL
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F452-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18F242-ISO PDF datasheet #2
- PIC18F242-ISO PDF datasheet #3
- PIC18F242-ISO PDF datasheet #4
- PIC18F242-ISO PDF datasheet #5
- PIC18F242-ISO PDF datasheet #6
- PIC18LF242-ISO PDF datasheet #7
- PIC18F452-EP PDF datasheet #8
- Current page: 180 of 332
- Download datasheet (6Mb)
PIC18FXX2
16.3.2
Once Synchronous mode is selected, reception is
enabled
(RCSTA<5>), or enable bit CREN (RCSTA<4>). Data is
sampled on the RC7/RX/DT pin on the falling edge of
the clock. If enable bit SREN is set, only a single word
is received. If enable bit CREN is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
To set up a Synchronous Master Reception:
1.
2.
3.
TABLE 16-9:
FIGURE 16-8:
DS39564C-page 178
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
SPBRG
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Reception.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits clear.
Name
RC7/RX/DT pin
RC6/TX/CK pin
Initialize the SPBRG register for the appropriate
baud rate (Section 16.1).
Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
Ensure bits CREN and SREN are clear.
Note:
(Interrupt)
CREN bit
Write to
bit SREN
SREN bit
RCIF bit
RXREG
by
Read
USART SYNCHRONOUS MASTER
RECEPTION
USART Receive Register
Baud Rate Generator Register
PSPIF
PSPIE
PSPIP
Timing diagram demonstrates Sync Master mode with bit SREN = '1' and bit BRGH = '0'.
SPEN
CSRC
GIEH
Bit 7
GIE/
setting
Q2
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
(1)
(1)
(1)
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
'0'
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
PEIE/
GIEL
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
either
TMR0IE INT0IE
SREN
TXEN
RCIF
RCIE
RCIP
enable
Bit 5
bit0
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CREN ADDEN
SYNC
bit1
bit
TXIE
TXIP
Bit 4
TXIF
SREN
SSPIF
SSPIE
SSPIP
bit2
RBIE
Bit 3
—
TMR0IF INT0IF
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
bit3
BRGH
FERR
Bit 2
4.
5.
6.
7.
8.
9.
10. If any error occurred, clear the error by clearing
11. If using interrupts, ensure that the GIE and PEIE
If interrupts are desired, set enable bit RCIE.
If 9-bit reception is desired, set bit RX9.
If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
the enable bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
bit CREN.
bits in the INTCON register (INTCON<7:6>) are
set.
bit4
OERR
TRMT
Bit 1
bit5
RX9D
TX9D
RBIF
Bit 0
© 2006 Microchip Technology Inc.
bit6
0000 000x 0000 000u
0000 -00x 0000 -00x
0000 0000 0000 0000
0000 -010 0000 -010
0000 0000 0000 0000
POR, BOR
Value on
bit7
Q1 Q2 Q3 Q4
All Other
Value on
RESETS
'0'
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