ATMEGA64L-8MUR Atmel, ATMEGA64L-8MUR Datasheet - Page 19
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ATMEGA64L-8MUR
Manufacturer Part Number
ATMEGA64L-8MUR
Description
MCU AVR 64KB FLASH 8MHZ 64QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA64L-8MUR
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA64L-8MUR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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SRAM Data
Memory
2490Q–AVR–06/10
The ATmega64 supports two different configurations for the SRAM data memory as listed in
Table
Table 1. Memory Configurations
Figure 9
The ATmega64 is a complex microcontroller with more peripheral units than can be supported
within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the
Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instruc-
tions can be used. The Extended I/O space does not exist when the ATmega64 is in the
ATmega103 compatibility mode.
The first 4,352 data memory locations address both the Register File, the I/O memory, Extended
I/O memory, and the internal data SRAM. The first 32 locations address the Register File, the
next 64 location the standard I/O memory, then 160 locations of Extended I/O memory, and the
next 4,096 locations address the internal data SRAM.
In ATmega103 compatibility mode, the first 4,096 data memory locations address both the Reg-
ister File, the I/O memory and the internal data SRAM. The first 32 locations address the
Register File, the next 64 location the standard I/O memory, and the next 4,000 locations
address the internal data SRAM.
An optional external data SRAM can be used with the ATmega64. This SRAM will occupy an
area in the remaining address locations in the 64K address space. This area starts at the
address following the internal SRAM. The Register File, I/O, Extended I/O and internal SRAM
occupy the lowest 4,352 bytes in Normal mode, and the lowest 4,096 bytes in the ATmega103
compatibility mode (Extended I/O not present), so when using 64 Kbytes(65,536 bytes) of Exter-
nal memory, 61,184 Bytes of External memory are available in Normal mode, and 61,440 Bytes
in ATmega103 compatibility mode. See
how to take advantage of the external memory map.
When the addresses accessing the SRAM memory space exceeds the internal data memory
locations, the external data SRAM is accessed using the same instructions as for the internal
data memory access. When the internal data memories are accessed, the read and write strobe
pins (PG0 and PG1) are inactive during the whole access cycle. External SRAM operation is
enabled by setting the SRE bit in the MCUCR Register.
Accessing external SRAM takes one additional clock cycle per byte compared to access of the
internal SRAM. This means that the commands LD, ST, LDS, STS, LDD, STD, PUSH, and POP
take one additional clock cycle. If the Stack is placed in external SRAM, interrupts, subroutine
calls and returns take three clock cycles extra because the 2-byte Program Counter is pushed
and popped, and external memory access does not take advantage of the internal pipeline
memory access. When external SRAM interface is used with wait state, one-byte external
access takes two, three, or four additional clock cycles for one, two, and three wait states
respectively. Interrupt, subroutine calls and returns will need five, seven, or nine clock cycles
more than specified in the AVR Instruction Set manual for one, two, and three waitstates.
The five different addressing modes for the data memory cover: Direct, Indirect with Displace-
ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register
File, registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space.
Configuration
Normal mode
ATmega103 compatibility mode
1.
on
page 20
shows how the ATmega64 SRAM Memory is organized.
Internal SRAM
Data Memory
“External Memory Interface” on page 27
4096
4000
External SRAM
Data Memory
up to 64K
up to 64K
ATmega64(L)
for details on
19
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