ATMEGA644A-PU Atmel, ATMEGA644A-PU Datasheet - Page 223
![IC MCU AVR 64K FLASH 40PDIP](/photos/6/70/67049/453-40-dip_sml.jpg)
ATMEGA644A-PU
Manufacturer Part Number
ATMEGA644A-PU
Description
IC MCU AVR 64K FLASH 40PDIP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA644A-PU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
ATmega
Core
AVR
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
JTAG, TWI, SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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8272A–AVR–01/10
Figure 20-13. Data Transfer in Master Receiver Mode
A START condition is sent by writing the following value to TWCR:
TWEN must be written to one to enable the 2-wire Serial Interface, TWSTA must be written to
one to transmit a START condition and TWINT must be set to clear the TWINT Flag. The TWI
will then test the 2-wire Serial Bus and generate a START condition as soon as the bus
becomes free. After a START condition has been transmitted, the TWINT Flag is set by hard-
ware, and the status code in TWSR will be 0x08 (See
MR mode, SLA+R must be transmitted. This is done by writing SLA+R to TWDR. Thereafter the
TWINT bit should be cleared (by writing it to one) to continue the transfer. This is accomplished
by writing the following value to TWCR:
When SLA+R have been transmitted and an acknowledgement bit has been received, TWINT is
set again and a number of status codes in TWSR are possible. Possible status codes in Master
mode are 0x38, 0x40, or 0x48. The appropriate action to be taken for each of these status codes
is detailed in
when the TWINT Flag is set high by hardware. This scheme is repeated until the last byte has
been received. After the last byte has been received, the MR should inform the ST by sending a
NACK after the last received data byte. The transfer is ended by generating a STOP condition or
a repeated START condition. A STOP condition is generated by writing the following value to
TWCR:
A REPEATED START condition is generated by writing the following value to TWCR:
After a repeated START condition (state 0x10) the 2-wire Serial Interface can access the same
Slave again, or a new Slave without transmitting a STOP condition. Repeated START enables
164A/164PA/324A/324PA/644A/644PA/1284/1284P
TWCR
value
TWCR
value
TWCR
value
TWCR
value
SDA
SCL
Table 20-3 on page
TWINT
TWINT
TWINT
TWINT
1
1
1
1
Device 1
RECEIVER
MASTER
TWEA
TWEA
TWEA
TWEA
X
X
X
X
TRANSMITTER
Device 2
SLAVE
TWSTA
TWSTA
TWSTA
TWSTA
224. Received data can be read from the TWDR Register
0
1
0
1
Device 3
TWSTO
TWSTO
TWSTO
TWSTO
0
0
1
0
........
Table 20-2 on page
TWWC
TWWC
TWWC
TWWC
Device n
X
X
X
X
V
CC
TWEN
TWEN
TWEN
TWEN
1
1
1
1
R1
221). In order to enter
R2
–
0
–
0
–
0
–
0
TWIE
TWIE
TWIE
TWIE
X
X
X
X
223
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